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公开(公告)号：US20240037028A1
公开(公告)日：2024-02-01
申请号：US18082693
申请日：2022-12-16
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Kedar CHITNIS , Mihir Narendra MODY , Prithvi Shankar YEYYADI ANANTHA , Sriramakrishnan GOVINDARAJAN , Mohd FAROOQUI , Shailesh GHOTGALKAR
IPC: G06F12/02
CPC classification number: G06F12/0292
Abstract: In an example, a method includes storing code for a first central processing unit (CPU) executing a first application in a first region of a memory, and storing code for a second CPU executing a second application in a second region of the memory. The method includes storing shared code for the first CPU and the second CPU in a third region of the memory. The method includes storing read-write data for the first CPU in a fourth region of the memory and storing read-write data for the second CPU in a fifth region of the memory. The method includes translating a first address from a first unique address space for the first CPU to a shared address space in the third region, and translating a second address from a second unique address space for the second CPU to the shared address space in the third region.
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公开(公告)号：US20240428365A1
公开(公告)日：2024-12-26
申请号：US18826385
申请日：2024-09-06
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Mihir Narendra MODY , Niraj NANDAN , Ankur ANKUR , Mayank MANGLA , Prithvi Shankar YEYYADI ANANTHA
Abstract: A technique including receiving an image stream for processing; processing the received image stream in a real time mode of operation; outputting an indication that an image processing pipeline has begun processing the received image stream; receiving, in response to the indication, first configuration information associated with test data for testing the image processing pipeline; switching the image processing pipeline to a non-real time mode of operation to process the test data based on the first configuration information during a vertical blanking period of the received image stream; loading the test data from an external memory; switching an input of the image processing pipeline from the image stream to the test data; determining a checksum based on the processed test data; comparing the determined checksum to an expected checksum to determine that the test data was successfully processed; and outputting an indication that the test data was successfully processed.
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公开(公告)号：US20240248839A1
公开(公告)日：2024-07-25
申请号：US18426053
申请日：2024-01-29
Applicant: TEXAS INSTRUMENTS INCORPORATED
IPC: G06F12/02
CPC classification number: G06F12/0246 , G06F2212/7201
Abstract: An Adaptive Memory Mirroring Performance Accelerator (AMMPA) includes a transaction handling block that dynamically maps the most frequently accessed memory regions into faster access memory. The technique creates shadow copies of the most frequently accessed memory regions in the faster access memory, which is associated with lower latency. The regions for which shadow copies are provided are updated dynamically based on use. The technique is flexible for different memory hierarchies.
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公开(公告)号：US20250117326A1
公开(公告)日：2025-04-10
申请号：US18987237
申请日：2024-12-19
Applicant: TEXAS INSTRUMENTS INCORPORATED
IPC: G06F12/02
Abstract: An Adaptive Memory Mirroring Performance Accelerator (AMMPA) includes a transaction handling block that dynamically maps the most frequently accessed data segments into faster access memory. The technique creates shadow copies of the most frequently accessed data segments in the faster access memory, which is associated with lower latency. Access frequencies of the data segments for which shadow copies are provided are updated dynamically based on use. The technique is flexible for different memory hierarchies.
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公开(公告)号：US20230326002A1
公开(公告)日：2023-10-12
申请号：US18333151
申请日：2023-06-12
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Mihir Narendra MODY, JR. , Veeramanikandan RAJU , Niraj NANDAN , Samuel Paul VISALLI , Jason A.T. JONES , Kedar Satish CHITNIS , Gregory Raymond SHURTZ , Prithvi Shankar YEYYADI ANANTHA , Sriramakrishnan GOVINDARAJAN
CPC classification number: G06T7/0002 , G06T1/20 , G06T3/40 , H04N17/00 , G06T7/97 , G06T2207/10016 , G05B23/0259
Abstract: Systems, methods and devices that improve fault detection capability of an imaging/vision hardware accelerator are provided. One such system includes a hardware accelerator, a signature generator, a signature processor, and a controller. These components cooperate to generate first and second output frames based on first and second reference frames, respectively; generate a third output frame based on a use-case frame; generate first and second image signatures based on the first and second output frames, respectively; compare the first image signature to a stored first reference image signature and output a first result; and compare the second image signature to a stored second reference image signature and output a second result. The controller determines, based on the results, whether the hardware accelerator has a fault at either a first time or a second time. When no fault is detected at either time, the controller analyzes the use-case frame for designation as an adaptive reference frame.
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Patent Agency Ranking
公开(公告)号：US20230161675A1
公开(公告)日：2023-05-25
申请号：US18151543
申请日：2023-01-09
Applicant: Texas Instruments Incorporated
IPC: G06F11/14
CPC classification number: G06F11/1497 , G06F2201/87
Abstract: An electronic device, comprising: a first component configured to transmit a first set of data to a second component by providing a first memory request specifying the first set of data for and an input memory address, and a transaction tracking unit coupled to a first transport interface, the transaction tracking unit configured to: receive the first memory request; transmit a second memory request that specifies at least a first portion of the first set of data, via the first transport interface, to the second component; receive a response to the second memory request from the second component; determine that the response corresponds to the second memory request; and provide, to the first component, an output response based on the received response to the second memory request.
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公开(公告)号：US20240427717A1
公开(公告)日：2024-12-26
申请号：US18819007
申请日：2024-08-29
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Mihir Narendra MODY , Ankur ANKUR , Vivek Vilas DHANDE , Kedar Satish CHITNIS , Niraj NANDAN , Brijesh JADAV , Shyam JAGANNATHAN , Prithvi Shankar YEYYADI ANANTHA , Santhanakrishnan Narayanan NARAYANAN
Abstract: Systems and methods in which trace data is efficiently managed are provided. An example system includes a memory, a first interface, and a processing resource communicably coupled to the first interface and to the memory. The processing resource includes a buffer, and a first controller to transmit a set of data from the buffer with associated trace information for the set of data to the memory. A second controller transmits the set of data with the associated trace information from the memory to a second interface.
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公开(公告)号：US20230267084A1
公开(公告)日：2023-08-24
申请号：US17677638
申请日：2022-02-22
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Mihir Narendra MODY, JR. , Ankur ANKUR , Vivek Vilas DHANDE , Kedar Satish CHITNIS , Niraj NANDAN , Brijesh JADAV , Shyam JAGANNATHAN , Prithvi Shankar YEYYADI ANANTHA , Santhanakrishnan Narayanan NARAYANAN
CPC classification number: G06F13/28 , G06F13/1673 , G06F13/4221 , G06F15/7807 , G06F9/4881
Abstract: A system-on-chip (SoC) in which trace data is managed includes a first memory device, a first interface to couple the first memory to a second memory external to the system-on-chip, and a first processing resource coupled to the first interface and the first memory device. The first processing resource includes a data buffer and a first direct access memory (DMA) controller. The first DMA controller transmits data from the data buffer to the first interface over a first channel, and transmits the data from the data buffer with associated trace information for the data to the first memory device over a second channel.
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公开(公告)号：US20220391776A1
公开(公告)日：2022-12-08
申请号：US17342037
申请日：2021-06-08
Applicant: Texas Instruments Incorporated
Inventor： Mihir Narendra MODY , Kumar DESAPPAN , Kedar Satish CHITNIS , Pramod Kumar SWAMI , Kevin Patrick LAVERY , Prithvi Shankar YEYYADI ANANTHA , Shyam JAGANNATHAN
Abstract: Techniques for executing machine learning (ML) models including receiving an indication to run a ML model, receiving synchronization information for organizing the running of the ML model with other ML models, determining, based on the synchronization information, to delay running the ML model, delaying the running of the ML model, determining, based on the synchronization information, a time to run the ML model; and running the ML model at the time.
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公开(公告)号：US20200074287A1
公开(公告)日：2020-03-05
申请号：US16556733
申请日：2019-08-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Mihir Narendra MODY , Prithvi Shankar YEYYADI ANANTHA
Abstract: A hardware neural network engine which uses checksums of the matrices used to perform the neural network computations. For fault correction, expected checksums are compared with checksums computed from the matrix developed from the matrix operation. The expected checksums are developed from the prior stage of the matrix operations or from the prior stage of the matrix operations combined with the input matrices to a matrix operation. This use of checksums allows reading of the matrices from memory, the dot product of the matrices and the accumulation of the matrices to be fault corrected without triplication of the matrix operation hardware and extensive use of error correcting codes. The nonlinear stage of the neural network computation is done using triplicated nonlinear computational logic. Fault detection is done in a similar manner, with fewer checksums needed and correction logic removed as compared to the fault correction operation.
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