公开(公告)号：US20240429275A1

公开(公告)日：2024-12-26

申请号：US18776479

申请日：2024-07-18

Applicant: Texas Instruments Incorporated

Inventor： Abbas Ali ,  Rajni J. Aggarwal ,  Steven J. Adler ,  Eugene C. Davis

IPC: H01L29/06 ,  H01L21/265 ,  H01L21/761 ,  H01L21/762 ,  H01L21/763

Abstract: An electronic device comprises a semiconductor substrate including majority carrier dopants of a first conductivity type, a semiconductor surface layer including majority carrier dopants of a second conductivity type, field oxide that extends on the semiconductor surface layer, and an isolation structure. The isolation structure includes a trench that extends through the semiconductor surface layer and into one of the semiconductor substrate and a buried layer of the semiconductor substrate, and polysilicon including majority carrier dopants of the second conductivity type, the polysilicon fills the trench to a side of the semiconductor surface layer.

公开(公告)号：US12087813B2

公开(公告)日：2024-09-10

申请号：US17462880

申请日：2021-08-31

Applicant: Texas Instruments Incorporated

Inventor： Abbas Ali ,  Rajni J. Aggarwal ,  Steven J. Adler ,  Eugene C. Davis

IPC: H01L29/06 ,  H01L21/265 ,  H01L21/761 ,  H01L21/762 ,  H01L21/763

CPC classification number: H01L29/0649 ,  H01L21/26513 ,  H01L21/76286 ,  H01L21/763 ,  H01L21/761

Abstract: An electronic device comprises a semiconductor substrate including majority carrier dopants of a first conductivity type, a semiconductor surface layer including majority carrier dopants of a second conductivity type, field oxide that extends on the semiconductor surface layer, and an isolation structure. The isolation structure includes a trench that extends through the semiconductor surface layer and into one of the semiconductor substrate and a buried layer of the semiconductor substrate, and polysilicon including majority carrier dopants of the second conductivity type, the polysilicon fills the trench to a side of the semiconductor surface layer.

公开(公告)号：US09818740B2

公开(公告)日：2017-11-14

申请号：US15368958

申请日：2016-12-05

Applicant: Texas Instruments Incorporated

Inventor： Weidong Tian ,  YuGuo Wang ,  Tathagata Chatterjee ,  Rajni J. Aggarwal

IPC: H01L27/06 ,  H01L29/739 ,  H01L29/06 ,  H01L29/10 ,  H01L29/45 ,  H01L29/417 ,  H01L21/8249 ,  H01L27/092

CPC classification number: H01L27/0623 ,  H01L21/8249 ,  H01L27/092 ,  H01L29/0688 ,  H01L29/1004 ,  H01L29/41708 ,  H01L29/423 ,  H01L29/456 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/7395

Abstract: An integrated circuit includes an NMOS transistor, a PMOS transistor and a vertical bipolar transistor. The vertical bipolar transistor has an intrinsic base with a band barrier at least 25 meV high at a surface boundary of the intrinsic base, except at an emitter-base junction with an emitter, and except at a base-collector junction with a collector. The intrinsic base may be laterally surrounded by an extrinsic base with a higher dopant density than the intrinsic base, wherein a higher dopant density provides the band barrier at lateral surfaces of the intrinsic base. A gate may be disposed on a gate dielectric layer over a top surface boundary of the intrinsic base adjacent to the emitter. The gate is configured to accumulate the intrinsic base immediately under the gate dielectric layer, providing the band barrier at the top surface boundary of the intrinsic base.

公开(公告)号：US09728581B2

公开(公告)日：2017-08-08

申请号：US14932949

申请日：2015-11-04

Applicant: Texas Instruments Incorporated

Inventor： Keith Ryan Green ,  Rajni J. Aggarwal ,  Ajit Sharma

IPC: H01L29/78 ,  H01L29/82 ,  H01L27/22 ,  H01L43/06 ,  H01L43/04 ,  H01L43/14

CPC classification number: H01L27/22 ,  H01L43/04 ,  H01L43/065 ,  H01L43/14

Abstract: A CMOS integrated circuit includes a Hall sensor having a Hall plate formed in a first isolation layer which is formed concurrently with a second isolation layer under a MOS transistor. A first shallow well with a conductivity type opposite from the first isolation layer is formed over, and extending to, the Hall plate. The first shallow well is formed concurrently with a second shallow well under the MOS transistor. The Hall sensor may be a horizontal Hall sensor for sensing magnetic fields oriented perpendicular to the top surface of the substrate of the integrated circuit, or may be a vertical Hall sensor for sensing magnetic fields oriented parallel to the top surface of the substrate of the integrated circuit.

公开(公告)号：US09362270B2

公开(公告)日：2016-06-07

申请号：US14645699

申请日：2015-03-12

Applicant: Texas Instruments Incorporated

Inventor： Rajni J. Aggarwal ,  Jau-Yuann Yang

IPC: H01L27/06 ,  H01L27/092 ,  H01L21/266 ,  H01L21/28 ,  H01L21/283 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/8238 ,  H01L49/02 ,  H01L29/49

CPC classification number: H01L28/20 ,  H01L21/266 ,  H01L21/28035 ,  H01L21/283 ,  H01L21/32053 ,  H01L21/32133 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L27/0629 ,  H01L27/092 ,  H01L29/4916 ,  H01L29/66583 ,  H01L29/6659

Abstract: An integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which has a body region that is implanted concurrently with the NSD layers of the NMOS transistors of the CMOS gates and concurrently with the PSD layers of the PMOS transistors of the CMOS gates, and has a resistor silicide block layer over the body region which is formed of separate material from the sidewall spacers on the CMOS gates. A process of forming an integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which implants the body region of the resistor concurrently with the NSD layers of the NMOS transistors of the CMOS gates and concurrently with the PSD layers of the PMOS transistors of the CMOS gates, and forms a resistor silicide block layer over the body region of separate material from the sidewall spacers on the CMOS gates.

公开(公告)号：US20190319068A1

公开(公告)日：2019-10-17

申请号：US16453468

申请日：2019-06-26

Applicant: Texas Instruments Incorporated

Inventor： Keith Ryan Green ,  Rajni J. Aggarwal ,  Ajit Sharma

IPC: H01L27/22 ,  H01L43/14 ,  H01L43/04 ,  H01L43/06

Abstract: A CMOS integrated circuit includes a Hall sensor having a Hall plate formed in a first isolation layer which is formed concurrently with a second isolation layer under a MOS transistor. A first shallow well with a conductivity type opposite from the first isolation layer is formed over, and extending to, the Hall plate. The first shallow well is formed concurrently with a second shallow well under the MOS transistor. The Hall sensor may be a horizontal Hall sensor for sensing magnetic fields oriented perpendicular to the top surface of the substrate of the integrated circuit, or may be a vertical Hall sensor for sensing magnetic fields oriented parallel to the top surface of the substrate of the integrated circuit.

公开(公告)号：US10396122B2

公开(公告)日：2019-08-27

申请号：US15639327

申请日：2017-06-30

Applicant: Texas Instruments Incorporated

Inventor： Keith Ryan Green ,  Rajni J. Aggarwal ,  Ajit Sharma

IPC: H01L27/22 ,  H01L43/04 ,  H01L43/06 ,  H01L43/14

Abstract: A CMOS integrated circuit includes a Hall sensor having a Hall plate formed in a first isolation layer which is formed concurrently with a second isolation layer under a MOS transistor. A first shallow well with a conductivity type opposite from the first isolation layer is formed over, and extending to, the Hall plate. The first shallow well is formed concurrently with a second shallow well under the MOS transistor. The Hall sensor may be a horizontal Hall sensor for sensing magnetic fields oriented perpendicular to the top surface of the substrate of the integrated circuit, or may be a vertical Hall sensor for sensing magnetic fields oriented parallel to the top surface of the substrate of the integrated circuit.

公开(公告)号：US09698211B2

公开(公告)日：2017-07-04

申请号：US15148004

申请日：2016-05-06

Applicant: Texas Instruments Incorporated

Inventor： Rajni J. Aggarwal ,  Jau-Yuann Yang

IPC: H01L21/28 ,  H01L49/02 ,  H01L27/06 ,  H01L27/092 ,  H01L21/266 ,  H01L21/283 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L28/20 ,  H01L21/266 ,  H01L21/28035 ,  H01L21/283 ,  H01L21/32053 ,  H01L21/32133 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L27/0629 ,  H01L27/092 ,  H01L29/4916 ,  H01L29/66583 ,  H01L29/6659

Abstract: An integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which has a body region that is implanted concurrently with the NSD layers of the NMOS transistors of the CMOS gates and concurrently with the PSD layers of the PMOS transistors of the CMOS gates, and has a resistor silicide block layer over the body region which is formed of separate material from the sidewall spacers on the CMOS gates. A process of forming an integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which implants the body region of the resistor concurrently with the NSD layers of the NMOS transistors of the CMOS gates and concurrently with the PSD layers of the PMOS transistors of the CMOS gates, and forms a resistor silicide block layer over the body region of separate material from the sidewall spacers on the CMOS gates.

公开(公告)号：US20170301726A1

公开(公告)日：2017-10-19

申请号：US15639327

申请日：2017-06-30

Applicant: Texas Instruments Incorporated

Inventor： Keith Ryan Green ,  Rajni J. Aggarwal ,  Ajit Sharma

IPC: H01L27/22 ,  H01L43/04 ,  H01L43/06 ,  H01L43/14

CPC classification number: H01L27/22 ,  H01L43/04 ,  H01L43/065 ,  H01L43/14

Abstract: A CMOS integrated circuit includes a Hall sensor having a Hall plate formed in a first isolation layer which is formed concurrently with a second isolation layer under a MOS transistor. A first shallow well with a conductivity type opposite from the first isolation layer is formed over, and extending to, the Hall plate. The first shallow well is formed concurrently with a second shallow well under the MOS transistor. The Hall sensor may be a horizontal Hall sensor for sensing magnetic fields oriented perpendicular to the top surface of the substrate of the integrated circuit, or may be a vertical Hall sensor for sensing magnetic fields oriented parallel to the top surface of the substrate of the integrated circuit.

公开(公告)号：US09665675B2

公开(公告)日：2017-05-30

申请号：US14563361

申请日：2014-12-08

Applicant: Texas Instruments Incorporated

Inventor： Ashesh Parikh ,  Chi-Chien Ho ,  Thomas John Smelko ,  Rajni J. Aggarwal

IPC: G06F17/50 ,  H01L21/8234 ,  H01L21/66

CPC classification number: G06F17/5045 ,  G06F17/5063 ,  G06F17/5068 ,  G06F2217/12 ,  H01L21/823456 ,  H01L22/20 ,  H01L22/34 ,  Y02P90/265

Abstract: A method to adjust transistor gate geometries in a design data base to compensate for transistor-to-transistor active overlap of gate differences and to form a reticle. A method to adjust transistor geometries in a design data base to compensate for transistor-to-transistor active overlap of gate differences and to compensate for transistor turn on voltage drop off where the transistor gate crosses the isolation/active interface.