公开(公告)号：US09496313B2

公开(公告)日：2016-11-15

申请号：US14292198

申请日：2014-05-30

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann Edwards ,  Toan Tran ,  Jeffrey R. Debord ,  Ashesh Parikh ,  Bradley David Sucher

IPC: H01L29/66 ,  H01L27/16 ,  H01L35/04 ,  H01L21/265 ,  H01L27/06 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/16 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/823878 ,  H01L27/0617 ,  H01L27/092 ,  H01L29/34 ,  H01L35/04 ,  H01L35/32 ,  H01L35/34

Abstract: An integrated circuit containing CMOS transistors and an embedded thermoelectric device is formed by forming isolation trenches in a substrate, concurrently between the CMOS transistors and between thermoelectric elements of the embedded thermoelectric device. Dielectric material is formed in the isolation trenches to provide field oxide which laterally isolates the CMOS transistors and the thermoelectric elements. Germanium is implanted into the substrate in areas for the thermoelectric elements, and the substrate is subsequently annealed, to provide a germanium density of at least 0.10 atomic percent in the thermoelectric elements between the isolation trenches. The germanium may be implanted before the isolation trenches are formed, after the isolation trenches are formed and before the dielectric material is formed in the isolation trenches, and/or after the dielectric material is formed in the isolation trenches.

Abstract translation: 通过在CMOS晶体管之间和嵌入式热电元件的热电元件之间同时形成衬底中的隔离沟槽，形成包含CMOS晶体管和嵌入式热电元件的集成电路。 介电材料形成在隔离沟槽中，以提供横向隔离CMOS晶体管和热电元件的场氧化物。 在用于热电元件的区域中将锗植入衬底中，并且随后对衬底进行退火，以在隔离沟槽之间的热电元件中提供至少0.10原子％的锗密度。 在形成隔离沟槽之后，在形成隔离沟槽之后并且在隔离沟槽内形成电介质材料之前和/或在隔离沟槽中形成电介质材料之后，可以注入锗。

公开(公告)号：US09665675B2

公开(公告)日：2017-05-30

申请号：US14563361

申请日：2014-12-08

Applicant: Texas Instruments Incorporated

Inventor： Ashesh Parikh ,  Chi-Chien Ho ,  Thomas John Smelko ,  Rajni J. Aggarwal

IPC: G06F17/50 ,  H01L21/8234 ,  H01L21/66

CPC classification number: G06F17/5045 ,  G06F17/5063 ,  G06F17/5068 ,  G06F2217/12 ,  H01L21/823456 ,  H01L22/20 ,  H01L22/34 ,  Y02P90/265

Abstract: A method to adjust transistor gate geometries in a design data base to compensate for transistor-to-transistor active overlap of gate differences and to form a reticle. A method to adjust transistor geometries in a design data base to compensate for transistor-to-transistor active overlap of gate differences and to compensate for transistor turn on voltage drop off where the transistor gate crosses the isolation/active interface.

公开(公告)号：US09853086B2

公开(公告)日：2017-12-26

申请号：US15350694

申请日：2016-11-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Henry Litzmann Edwards ,  Toan Tran ,  Jeffrey R. Debord ,  Ashesh Parikh ,  Bradley David Sucher

IPC: H01L29/66 ,  H01L27/16 ,  H01L35/04 ,  H01L21/265 ,  H01L21/8238 ,  H01L27/06 ,  H01L29/34 ,  H01L35/32 ,  H01L35/34 ,  H01L27/092

CPC classification number: H01L27/16 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/823878 ,  H01L27/0617 ,  H01L27/092 ,  H01L29/34 ,  H01L35/04 ,  H01L35/32 ,  H01L35/34

Abstract: In described examples, an embedded thermoelectric device is formed by forming isolation trenches in a substrate, concurrently between CMOS transistors and between thermoelectric elements of the embedded thermoelectric device. Dielectric material is formed in the isolation trenches to provide field oxide which laterally isolates the CMOS transistors and the thermoelectric elements. Germanium is implanted into the substrate in areas for the thermoelectric elements, and the substrate is subsequently annealed, to provide a germanium density of at least 0.10 atomic percent in the thermoelectric elements between the isolation trenches. The germanium may be implanted before the isolation trenches are formed, after the isolation trenches are formed and before the dielectric material is formed in the isolation trenches, and/or after the dielectric material is formed in the isolation trenches.

公开(公告)号：US20150349022A1

公开(公告)日：2015-12-03

申请号：US14292198

申请日：2014-05-30

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann Edwards ,  Toan Tran ,  Jeffrey R. Debord ,  Ashesh Parikh ,  Bradley David Sucher

IPC: H01L27/16 ,  H01L21/265 ,  H01L21/8238 ,  H01L35/04 ,  H01L27/092

CPC classification number: H01L27/16 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/823878 ,  H01L27/0617 ,  H01L27/092 ,  H01L29/34 ,  H01L35/04 ,  H01L35/32 ,  H01L35/34

Abstract: An integrated circuit containing CMOS transistors and an embedded thermoelectric device is formed by forming isolation trenches in a substrate, concurrently between the CMOS transistors and between thermoelectric elements of the embedded thermoelectric device. Dielectric material is formed in the isolation trenches to provide field oxide which laterally isolates the CMOS transistors and the thermoelectric elements. Germanium is implanted into the substrate in areas for the thermoelectric elements, and the substrate is subsequently annealed, to provide a germanium density of at least 0.10 atomic percent in the thermoelectric elements between the isolation trenches. The germanium may be implanted before the isolation trenches are formed, after the isolation trenches are formed and before the dielectric material is formed in the isolation trenches, and/or after the dielectric material is formed in the isolation trenches.

Abstract translation: 通过在CMOS晶体管之间和嵌入式热电元件的热电元件之间同时形成衬底中的隔离沟槽，形成包含CMOS晶体管和嵌入式热电元件的集成电路。 介电材料形成在隔离沟槽中，以提供横向隔离CMOS晶体管和热电元件的场氧化物。 在用于热电元件的区域中将锗植入衬底中，并且随后对衬底进行退火，以在隔离沟槽之间的热电元件中提供至少0.10原子％的锗密度。 在形成隔离沟槽之后，在形成隔离沟槽之后并且在隔离沟槽内形成电介质材料之前和/或在隔离沟槽中形成电介质材料之后，可以注入锗。

公开(公告)号：US08806388B2

公开(公告)日：2014-08-12

申请号：US13849227

申请日：2013-03-22

Applicant: Texas Instruments Incorporated

Inventor： Ashesh Parikh

IPC: G06F17/50 ,  G03F7/20 ,  G03F1/36

CPC classification number: G06F17/50 ,  G03F1/36 ,  G03F7/705 ,  G03F7/70516 ,  G03F7/70625 ,  G03F7/70641

Abstract: A method of computational lithography includes collecting a critical dimension (CD) data set including CD data from printing a test structure including a set of gratings which provide a plurality of feature types including different ratios of line width to space width, where the printing includes a range of different focus values. The CD data is weighted to form a weighted CD data set using a weighting algorithm (WA) that assigns cost weights to the CD data based its feature type and its magnitude of CD variation with respect to a CD value for its feature type at a nominal focus (nominal CD). The WA algorithm reduces a value of the cost weight as the magnitude of variation increases. At least one imaging parameter is extracted from the weighted CD data set. A computational lithography model is automatically calibrated using the imaging parameter(s).

Abstract translation: 一种计算光刻方法包括收集包括CD数据的关键尺寸（CD）数据集，其中包括一组测试结构，该测试结构包括提供包括不同比例的线宽与空间宽度的多种特征类型的一组光栅，其中打印包括 范围不同的焦点值。 对CD数据进行加权，以使用加权算法（WA）来加权CD数据集，该权重算法（WA）根据其特征类型及其相对于其名义上的特征类型的CD值的CD变化的大小分配CD数据的成本加权 焦点（标称CD）。 WA算法随着变化幅度的增加而降低成本重量的值。 从加权的CD数据集中提取至少一个成像参数。 使用成像参数自动校准计算光刻模型。

公开(公告)号：US10339251B2

公开(公告)日：2019-07-02

申请号：US15495016

申请日：2017-04-24

Applicant: Texas Instruments Incorporated

Inventor： Ashesh Parikh ,  Chi-Chien Ho ,  Thomas John Smelko ,  Rajni J. Aggarwal

IPC: G06F17/50 ,  H01L21/66 ,  H01L21/8234

Abstract: A method to adjust transistor gate geometries in a design data base to compensate for transistor-to-transistor active overlap of gate differences and to form a reticle. A method to adjust transistor geometries in a design data base to compensate for transistor-to-transistor active overlap of gate differences and to compensate for transistor turn on voltage drop off where the transistor gate crosses the isolation/active interface.

公开(公告)号：US20170062518A1

公开(公告)日：2017-03-02

申请号：US15350694

申请日：2016-11-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Henry Litzmann Edwards ,  Toan Tran ,  Jeffrey R. Debord ,  Ashesh Parikh ,  Bradley David Sucher

IPC: H01L27/16 ,  H01L35/32 ,  H01L21/8238 ,  H01L21/265 ,  H01L35/04 ,  H01L35/34

CPC classification number: H01L27/16 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/823878 ,  H01L27/0617 ,  H01L27/092 ,  H01L29/34 ,  H01L35/04 ,  H01L35/32 ,  H01L35/34

Abstract: In described examples, an embedded thermoelectric device is formed by forming isolation trenches in a substrate, concurrently between CMOS transistors and between thermoelectric elements of the embedded thermoelectric device. Dielectric material is formed in the isolation trenches to provide field oxide which laterally isolates the CMOS transistors and the thermoelectric elements. Germanium is implanted into the substrate in areas for the thermoelectric elements, and the substrate is subsequently annealed, to provide a germanium density of at least 0.10 atomic percent in the thermoelectric elements between the isolation trenches. The germanium may be implanted before the isolation trenches are formed, after the isolation trenches are formed and before the dielectric material is formed in the isolation trenches, and/or after the dielectric material is formed in the isolation trenches.

Abstract translation: 在所述实施例中，通过在CMOS晶体管之间以及嵌入式热电元件的热电元件之间同时形成衬底中的隔离沟槽来形成嵌入式热电元件。 介电材料形成在隔离沟槽中，以提供横向隔离CMOS晶体管和热电元件的场氧化物。 在用于热电元件的区域中将锗植入衬底中，并且随后对衬底进行退火，以在隔离沟槽之间的热电元件中提供至少0.10原子％的锗密度。 在形成隔离沟槽之后，在形成隔离沟槽之后并且在隔离沟槽内形成电介质材料之前和/或在隔离沟槽中形成电介质材料之后，可以注入锗。

公开(公告)号：US08793626B2

公开(公告)日：2014-07-29

申请号：US13849195

申请日：2013-03-22

Applicant: Texas Instruments Incorporated

Inventor： Ashesh Parikh ,  Chi-Chien Ho ,  Thomas John Smelko

IPC: G06F17/50

CPC classification number: G06F17/50 ,  G03F1/36 ,  G03F7/70441 ,  G03F7/705 ,  G03F7/70625 ,  G03F7/70641

Abstract: A method of computational lithography includes providing through-focus critical dimension (CD) curves at a range of different focus values (Bossung curves) for a plurality of feature types that include different ratios of line width to space width. Using software run on a computing device, it is determined if there is at least one marginal feature type from the plurality of feature types based an image tool capability and a predetermined process specification affected by at least one of the plurality of feature types. Provided a marginal feature type is determined to be present, at least the marginal feature type(s) is upsized. A degree of upsizing increases as a curvature of the Bossung curves increases. A computational lithography model is compiled including the upsizing.

Abstract translation: 计算光刻的方法包括在包括不同比例的线宽与空间宽度的多种特征类型的不同聚焦值（Bossung曲线）的范围内提供聚焦临界尺寸（CD）曲线。 使用在计算设备上运行的软件，基于图像工具能力和受多个特征类型中的至少一个特征类型影响的预定处理规范来确定是否存在来自多个特征类型的至少一个边缘特征类型。 如果边缘特征类型被确定为存在，则至少边际特征类型被增大。 随着Bossung曲线的曲率增加，一定程度的大小增加。 编制计算光刻模型，包括大型化。