公开(公告)号：US12266596B2

公开(公告)日：2025-04-01

申请号：US17227722

申请日：2021-04-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rajen Manicon Murugan ,  Yiqi Tang

IPC: H01L23/498 ,  H01L21/48 ,  H02M1/00

Abstract: A semiconductor device includes a die with a power converter module. The power converter module includes an output port and a return port. The semiconductor device also includes a connection assembly that includes pads configured to be coupled to circuit components of a printed circuit board (PCB). The connection assembly also includes a first layer patterned to include a first trace that is coupled to one of the output port and the return port and a second trace that is coupled to the other of the output port and return port. A second layer of the connection assembly is patterned to provide a first via between the first trace and a third layer and a second via between the first trace and the third layer. The third layer is patterned to provide a portion of a first conductive path and a portion of a second conductive path.

公开(公告)号：US11901271B2

公开(公告)日：2024-02-13

申请号：US18148627

申请日：2022-12-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yiqi Tang ,  Liang Wan ,  William Todd Harrison ,  Manu Joseph Prakuzhy ,  Rajen Manicon Murugan

IPC: H01L23/495 ,  H02M3/158 ,  H01L23/00

CPC classification number: H01L23/49575 ,  H01L23/49524 ,  H01L23/49562 ,  H01L24/32 ,  H02M3/158 ,  H01L2224/32245

Abstract: In some examples, a direct current (DC)-DC power converter package comprises a controller, a conductive member, and a first field effect transistor (FET) coupled to the controller and having a first source and a first drain, the first FET coupled to a first portion of the conductive member. The package also comprises a second FET coupled to the controller and having a second source and a second drain, the second FET coupled to a second portion of the conductive member, the first and second portions of the conductive member being non-overlapping in a horizontal plane. The first and second FETs are non-overlapping.

公开(公告)号：US11837775B2

公开(公告)日：2023-12-05

申请号：US17539110

申请日：2021-11-30

Applicant: Texas Instruments Incorporated

Inventor： Yiqi Tang ,  Rajen Manicon Murugan ,  Juan Alejandro Herbsommer

IPC: H01Q1/22 ,  H01L23/31 ,  H05K1/02 ,  H01L23/66

CPC classification number: H01Q1/2283 ,  H01L23/3114 ,  H01L23/66 ,  H05K1/0237 ,  H01L2223/6677

Abstract: A described example includes: an antenna formed in a first conductor layer on a device side surface of a multilayer package substrate, the multilayer package substrate including conductor layers spaced from one another by dielectric material and coupled to one another by conductive vertical connection layers, the multilayer package substrate having a board side surface opposite the device side surface; and a semiconductor die mounted to the device side surface of the multilayer package substrate spaced from and coupled to the antenna.

公开(公告)号：US20230245982A1

公开(公告)日：2023-08-03

申请号：US18295192

申请日：2023-04-03

Applicant: Texas Instruments Incorporated

Inventor： Jie Chen ,  Yiqi Tang ,  Rajen Murugan ,  Liang Wan

IPC: H01L23/552 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/552 ,  H01L23/49822 ,  H01L24/32 ,  H01L24/20 ,  H01L24/83 ,  H01L24/19 ,  H01L2924/1426 ,  H01L2224/32225 ,  H01L2224/2101 ,  H01L2924/3025 ,  H01L2924/14253 ,  H01L2924/13091

Abstract: A semiconductor package includes a multilayer package substrate including a first layer including a first dielectric and first metal layer including a first metal trace and a second layer including a second dielectric layer. An integrated circuit (IC) die includes bond pads, with a bottom side of the IC die attached to the first metal trace. Metal pillars are through the second dielectric layer connecting to the first metal trace. A third layer on the second layer includes a third dielectric layer on the second layer extending to a bottom side of the semiconductor package, and a second metal layer including second metal traces including inner second metal traces connected to the bond pads and outer second metal traces over the metal pillars, and filled vias providing externally accessible contact pads that connect the second metal traces to a bottom side of the semiconductor package.

公开(公告)号：US20230215811A1

公开(公告)日：2023-07-06

申请号：US17569724

申请日：2022-01-06

Applicant: Texas Instruments Incorporated

Inventor： Yiqi Tang ,  Rajen Murugan ,  Jie Chen

IPC: H01L23/552 ,  H03K17/042 ,  H01L23/495 ,  H01L25/00

CPC classification number: H01L23/552 ,  H03K17/04206 ,  H01L23/49503 ,  H01L25/50 ,  H01L23/49537 ,  H01L23/49575 ,  H01L24/48

Abstract: A multi-channel gate driver package includes a leadframe including a first, second, and third die pad. A transmitter die includes first and second transmitter signal bond pads, a first receiver die including a second signal bond pad, and a second receiver die including a third signal bond pad. A bond wire is between the first transmitter signal bond pad and the second signal bond pad, and between the second transmitter signal bond pad and third signal bond pad. A ring shield is around the respective signal bond pads. A downbond is from the second ring shield to the second die pad, and from the third ring shield to the third die pad. A connection connects the first and second transmitter ring shield to at least one ground pin of the package. The second and third die pad each include a direct integral connection to the ground pin.

公开(公告)号：US20230207509A1

公开(公告)日：2023-06-29

申请号：US18171028

申请日：2023-02-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yiqi Tang ,  Naweed Anjum ,  Liang Wan ,  Michael Gerald Amaro

IPC: H01L23/00 ,  H01L23/58 ,  H01L23/498 ,  H01L21/56

CPC classification number: H01L24/24 ,  H01L21/568 ,  H01L23/58 ,  H01L23/49861 ,  H01L24/82 ,  H01L24/92 ,  H01L2224/24195 ,  H01L2224/24227 ,  H01L2224/24265 ,  H01L2224/32227 ,  H01L2224/82005 ,  H01L2224/82101 ,  H01L2224/92244

Abstract: A semiconductor package includes a first layer including a semiconductor die embedded within a dielectric substrate, and a first set of metal pillars extending through the dielectric substrate, a second layer stacked on the first layer, the second layer including a metal trace patterned on the dielectric substrate of the first layer, a passive component including at least one capacitor or resistor electrically coupled to the metal trace, and a second set of metal pillars extending from the metal trace to an opposing side of the second layer, and a third layer stacked on the second layer, the third layer including at least one inductor electrically coupled to metal pillars of the second set of metal pillars.

公开(公告)号：US20230198170A1

公开(公告)日：2023-06-22

申请号：US18169682

申请日：2023-02-15

Applicant: Texas Instruments Incorporated

Inventor： Yiqi Tang ,  Rajen Manicon Murugan

IPC: H01Q23/00 ,  H01L23/66 ,  H01Q1/22

CPC classification number: H01Q23/00 ,  H01L23/66 ,  H01Q1/2283

Abstract: An AIP includes a package substrate including a top layer including a top metal layer including a first antenna type and a second antenna type, and a bottom layer including a bottom dielectric and a metal layer including a first and second contact pad and filled vias, and an IC embedded therein. Bond pads of an IC are coupled by a connection including≥1 filled via for connecting to the top and/or bottom metal layer. A first metal pillar is between the first contact pad and first antenna, and a second metal pillar is between the second contact pad and second antenna. A first filled via is coupled to the first metal pillar providing a transmission line from the first contact pad to the first antenna. A second filled via is coupled to the first metal pillar providing a transmission line from the second contact pad to the second antenna.

公开(公告)号：US11587891B2

公开(公告)日：2023-02-21

申请号：US17335010

申请日：2021-05-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yiqi Tang ,  Li Jiang ,  Rajen Manicon Murugan

IPC: H01L23/58 ,  H01L23/552 ,  H01L23/00

Abstract: In examples, a semiconductor package comprises a ceramic substrate and first and second metal layers covered by the ceramic substrate. The first metal layer is configured to carry signals at least in a 20 GHz to 28 GHz frequency range. The package comprises a semiconductor die positioned above the first and second metal layers and coupled to the first metal layer. The package comprises a ground shield positioned in a horizontal plane between the semiconductor die and the first metal layer, the ground shield including an orifice above a portion of the first metal layer. The package includes a metal seal ring coupled to a top surface of the ceramic substrate, the metal seal ring having a segment that is vertically aligned with a segment of the ground shield. The segment of the ground shield is between the orifice of the ground shield and a horizontal center of the ground shield. The package comprises a metal lid coupled to a top surface of the metal seal ring.

公开(公告)号：US20220384353A1

公开(公告)日：2022-12-01

申请号：US17500086

申请日：2021-10-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yiqi Tang ,  Rajen Manicon Murugan ,  Liang Wan ,  Makarand Ramkrishna Kulkarni ,  Jie Chen ,  Steven Alfred Kummerl

IPC: H01L23/538 ,  H01L23/00 ,  H01L21/48

Abstract: A semiconductor package includes a first layer including a semiconductor die and a shunt embedded within a first dielectric substrate layer, and metal pillars extending therethrough. The semiconductor package further includes a second layer stacked on the first layer, the second layer including a metal trace patterned on the first dielectric substrate layer, and a second dielectric substrate layer over the metal trace. The metal trace electrically connects a first portion of the shunt to a first metal pillar of the metal pillars and electrically connects a second portion of the shunt to a second metal pillar of the metal pillars. The semiconductor package further includes a base layer opposite the second layer relative the first layer, the base layer forming exposed electrical contact pads for the semiconductor package, the electrical contact pads providing electrical connections to the shunt, the metal pillars, and the semiconductor die.

公开(公告)号：US20220376378A1

公开(公告)日：2022-11-24

申请号：US17736653

申请日：2022-05-04

Applicant: Texas Instruments Incorporated

Inventor： Yiqi Tang ,  Rajen Manicon Murugan

IPC: H01Q1/22 ,  H01Q9/04 ,  H01Q13/02 ,  H01Q19/10 ,  H01L23/66

Abstract: An example semiconductor package comprises a patch antenna formed in a first conductor layer of a multilayer package substrate. The multilayer package substrate comprises conductor layers spaced from one another by dielectric material and coupled to one another by conductive vertical connection layers. The multilayer package substrate has a board side surface opposite a device side surface. The semiconductor package further comprises a semiconductor die mounted to the device side surface of the multilayer package substrate spaced from and coupled to the patch antenna. An antenna horn is mounted to the device side surface and aligned with the patch antenna using a mounting structure. The semiconductor package further comprises a reflector formed on a second conductor layer in the multilayer package substrate. The second conductor layer is positioned closer to the board side surface of the multilayer package substrate compared to the patch antenna.