公开(公告)号：US12293924B2

公开(公告)日：2025-05-06

申请号：US18415411

申请日：2024-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng Chen ,  Wei-Ting Chien ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: G03F7/20 ,  G03F7/00 ,  H01L21/027 ,  H01L21/32

Abstract: A method of exposing a wafer to a high-tilt angle ion beam and an apparatus for performing the same are disclosed. In an embodiment, a method includes forming a patterned mask layer over a wafer, the patterned mask layer including a patterned mask feature; exposing the wafer to an ion beam, a surface of the wafer being tilted at a tilt angle with respect to the ion beam; and moving the wafer along a scan line with respect to the ion beam, a scan angle being defined between the scan line and an axis perpendicular to an axis of the ion beam, a difference between the tilt angle and the scan angle being less than 50°.

公开(公告)号：US20230061485A1

公开(公告)日：2023-03-02

申请号：US17463000

申请日：2021-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng Chen ,  Chun-Hung Wu ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo ,  Chun-Yen Chang ,  Chih-Kai Yang ,  Yu-Tien Shen ,  Ya Hui Chang

IPC: H01L21/027 ,  H01L21/311 ,  H01L21/768

Abstract: A method for forming a semiconductor device is provided. In some embodiments, the method includes forming a target layer over a semiconductor substrate, forming a carbon-rich hard masking layer over the target layer, patterning features in the carbon-rich hard masking layer using an etching process, performing a directional ion beam trimming process on the features patterned in the carbon-rich hard masking layer, and patterning the target layer using the carbon-rich hard masking layer as a mask.

公开(公告)号：US20220367254A1

公开(公告)日：2022-11-17

申请号：US17871042

申请日：2022-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Shih Wang ,  Po-Nan Yeh ,  U-Ting Chiu ,  Chun-Neng Lin ,  Chia-Cheng Chen ,  Liang-Yin Chen ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: Semiconductor devices and methods of manufacture are described herein. A method includes forming an opening through an interlayer dielectric (ILD) layer to expose a contact etch stop layer (CESL) disposed over a conductive feature in a metallization layer. The opening is formed using photo sensitive materials, lithographic techniques, and a dry etch process that stops on the CESL. Once the CESL is exposed, a CESL breakthrough process is performed to extend the opening through the CESL and expose the conductive feature. The CESL breakthrough process is a flexible process with a high selectivity of the CESL to ILD layer. Once the CESL breakthrough process has been performed, a conductive fill material may be deposited to fill or overfill the opening and is then planarized with the ILD layer to form a contact plug over the conductive feature in an intermediate step of forming a semiconductor device.

公开(公告)号：US20240371688A1

公开(公告)日：2024-11-07

申请号：US18775995

申请日：2024-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Shih Wang ,  Po-Nan Yeh ,  U-Ting Chiu ,  Chun-Neng Lin ,  Chia-Cheng Chen ,  Liang-Yin Chen ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: Semiconductor devices and methods of manufacture are described herein. A method includes forming an opening through an interlayer dielectric (ILD) layer to expose a contact etch stop layer (CESL) disposed over a conductive feature in a metallization layer. The opening is formed using photo sensitive materials, lithographic techniques, and a dry etch process that stops on the CESL. Once the CESL is exposed, a CESL breakthrough process is performed to extend the opening through the CESL and expose the conductive feature. The CESL breakthrough process is a flexible process with a high selectivity of the CESL to ILD layer. Once the CESL breakthrough process has been performed, a conductive fill material may be deposited to fill or overfill the opening and is then planarized with the ILD layer to form a contact plug over the conductive feature in an intermediate step of forming a semiconductor device.

公开(公告)号：US11978677B2

公开(公告)日：2024-05-07

申请号：US17459164

申请日：2021-08-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng Chen ,  Chih-Kai Yang ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/66 ,  H01J37/20 ,  H01J37/22 ,  H01J37/304 ,  H01J37/317 ,  H01L21/265 ,  H01L23/544

CPC classification number: H01L22/20 ,  H01J37/20 ,  H01J37/22 ,  H01J37/3045 ,  H01J37/3171 ,  H01L21/265 ,  H01L23/544 ,  H01J2237/20214 ,  H01J2237/30438 ,  H01L2223/54426

Abstract: In an embodiment, a method includes: placing a wafer on an implanter platen, the wafer including alignment marks; measuring a position of the wafer by measuring positions of the alignment marks with one or more cameras; determining an angular displacement between the position of the wafer and a reference position of the wafer; and rotating the implanter platen by the angular displacement.

公开(公告)号：US11915942B2

公开(公告)日：2024-02-27

申请号：US17855216

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng Chen ,  Wei-Ting Chien ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: G03F7/20 ,  H01L21/32 ,  H01L21/027 ,  G03F7/00

CPC classification number: H01L21/32 ,  G03F7/70283 ,  H01L21/027

Abstract: A method of exposing a wafer to a high-tilt angle ion beam and an apparatus for performing the same are disclosed. In an embodiment, a method includes forming a patterned mask layer over a wafer, the patterned mask layer including a patterned mask feature; exposing the wafer to an ion beam, a surface of the wafer being tilted at a tilt angle with respect to the ion beam; and moving the wafer along a scan line with respect to the ion beam, a scan angle being defined between the scan line and an axis perpendicular to an axis of the ion beam, a difference between the tilt angle and the scan angle being less than 50°.

公开(公告)号：US20220406629A1

公开(公告)日：2022-12-22

申请号：US17720807

申请日：2022-04-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng Chen ,  Chih-Kai Yang ,  Chun-Liang Chen ,  Wei-Ting Chien ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/67 ,  G03F7/40

Abstract: In an embodiment, a pattern transfer processing chamber includes a pattern transfer processing chamber and a loading area external to the pattern transfer processing chamber. The loading area is configured to transfer a wafer to or from the pattern transfer processing chamber. The loading area comprises a first region including a loadport, a second region including a load-lock between the first region and the pattern transfer processing chamber, and an embedded baking chamber configured to heat a patterned photoresist on the wafer.

公开(公告)号：US20220367632A1

公开(公告)日：2022-11-17

申请号：US17872452

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Hao Liu ,  Huicheng Chang ,  Chia-Cheng Chen ,  Liang-Yin Chen ,  Kuo-Ju Chen ,  Chun-Hung Wu ,  Chang-Miao Liu ,  Huai-Tei Yang ,  Lun-Kuang Tan ,  Wei-Ming You

IPC: H01L29/08 ,  H01L29/167 ,  H01L29/78 ,  H01L21/02 ,  H01L21/285 ,  H01L29/66 ,  H01L21/265 ,  H01L29/417

Abstract: The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.

公开(公告)号：US10727226B2

公开(公告)日：2020-07-28

申请号：US15652719

申请日：2017-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng Chen ,  Chia-Ling Chan ,  Liang-Yin Chen ,  Huicheng Chang

IPC: H01L29/165 ,  H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/12 ,  H01L21/84

Abstract: A semiconductor device and a method for forming the same are provided. The semiconductor device includes a gate structure and a source/drain feature. The gate structure is positioned over a fin structure. The source/drain feature is positioned adjacent to the gate structure. A portion of the source/drain feature embedded in the fin structure has an upper sidewall portion adjacent to a top surface of the fin structure and a lower sidewall portion below the upper sidewall portion. A first curve radius of the upper sidewall portion is different from a second curve radius of the lower sidewall portion in a cross-sectional view substantially along the longitudinal direction of the fin structure.

公开(公告)号：US20190288068A1

公开(公告)日：2019-09-19

申请号：US16433374

申请日：2019-06-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Hao Liu ,  Huicheng Chang ,  Chia-Cheng Chen ,  Liang-Yin Chen ,  Kuo-Ju Chen ,  Chun-Hung Wu ,  Chang-Maio Liu ,  Huai-Tei Yang ,  Lun-Kuang Tan ,  Wei-Ming You

IPC: H01L29/08 ,  H01L21/265 ,  H01L21/02 ,  H01L29/66 ,  H01L29/167 ,  H01L29/78 ,  H01L21/285

Abstract: The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.