公开(公告)号：US10509071B2

公开(公告)日：2019-12-17

申请号：US15355446

申请日：2016-11-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Di Chuang ,  Tien-Chung Lee ,  Chiu-Hua Chung ,  Kang-Tai Peng

IPC: G01R31/28 ,  G01R1/073

Abstract: A method for probe card alignment is provided. The method includes providing a probe card with a plurality of probe needles having their distal ends on a reference plane. The method further includes providing a light from both the upper side and lower side of the reference plane. The method also includes using a camera to image the probe needles. In addition, the method includes performing a probe card alignment process according to the image generated by the camera.

公开(公告)号：US11145709B2

公开(公告)日：2021-10-12

申请号：US16439636

申请日：2019-06-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hong-Yang Chen ,  Tian Sheng Lin ,  Yi-Cheng Chiu ,  Hung-Chou Lin ,  Yi-Min Chen ,  Kuo-Ming Wu ,  Chiu-Hua Chung

IPC: H01L27/108 ,  H01L29/76 ,  H01L31/119 ,  H01L49/02 ,  H01L27/01 ,  H01L27/06

Abstract: A capacitor structure for a power semiconductor device includes a semiconductor substrate, an isolation insulating layer having a ring-shape and including an outer periphery and an inner periphery defining an opening region, a first electrode disposed on the isolation insulating layer, a dielectric layer disposed on the first electrode, and a second electrode disposed on the dielectric layer.

公开(公告)号：US20200058647A1

公开(公告)日：2020-02-20

申请号：US16662496

申请日：2019-10-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Karthick Murukesan ,  Wen-Chih Chiang ,  Chiu-Hua Chung ,  Chun Lin Tsai ,  Kuo-Ming Wu ,  Shiuan-Jeng Lin ,  Tien Sheng Lin ,  Yi-Min Chen ,  Hung-Chou Lin ,  Yi-Cheng Chiu

IPC: H01L27/07 ,  H01L21/8234 ,  H01L27/06 ,  H01L29/78 ,  H01L21/761

Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a bootstrap metal-oxide-semiconductor (MOS) device is integrated with a high voltage metal-oxide-semiconductor (HVMOS) device and a high voltage junction termination (HVJT) device. In some embodiments, a drift well is in the semiconductor substrate. The drift well has a first doping type and has a ring-shaped top layout. A first switching device is on the drift well. A second switching device is on the semiconductor substrate, at an indent in a sidewall the drift well. A peripheral well is in the semiconductor substrate and has a second doping type opposite the first doping type. The peripheral well surrounds the drift well, the first switching device, and the second switching device, and further separates the second switching device from the drift well and the first switching device.

公开(公告)号：US12062686B2

公开(公告)日：2024-08-13

申请号：US16991385

申请日：2020-08-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Guo-Jyun Luo ,  Chen-Chien Chang ,  Chiu-Hua Chung ,  Shiuan-Jeng Lin ,  Han-Zong Pan

IPC: H01L21/285 ,  H01L27/06 ,  H01L27/08 ,  H01L49/02

CPC classification number: H01L28/40 ,  H01L21/2855 ,  H01L27/0629 ,  H01L27/0805

Abstract: The present disclosure relates to a semiconductor device structure. The semiconductor device structure has a first conductive layer disposed over a substrate and a first capacitor dielectric layer comprising a first dielectric material disposed over the first conductive layer. A second conductive layer is over the first capacitor dielectric layer, a second capacitor dielectric layer comprising a second dielectric material is disposed over the second conductive layer, and a third conductive layer is over the second capacitor dielectric layer. A first barrier layer is disposed between an upper surface of the first conductive layer and a lower surface of the first capacitor dielectric layer.

公开(公告)号：US20200373380A1

公开(公告)日：2020-11-26

申请号：US16991385

申请日：2020-08-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Guo-Jyun Luo ,  Chen-Chien Chang ,  Chiu-Hua Chung ,  Shiuan-Jeng Lin ,  Han-Zong Pan

IPC: H01L49/02 ,  H01L27/08 ,  H01L27/06 ,  H01L21/285

Abstract: The present disclosure relates to a semiconductor device structure. The semiconductor device structure has a first conductive layer disposed over a substrate and a first capacitor dielectric layer comprising a first dielectric material disposed over the first conductive layer. A second conductive layer is over the first capacitor dielectric layer, a second capacitor dielectric layer comprising a second dielectric material is disposed over the second conductive layer, and a third conductive layer is over the second capacitor dielectric layer. A first barrier layer is disposed between an upper surface of the first conductive layer and a lower surface of the first capacitor dielectric layer.

公开(公告)号：US10679987B2

公开(公告)日：2020-06-09

申请号：US16128578

申请日：2018-09-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Karthick Murukesan ,  Wen-Chih Chiang ,  Chiu-Hua Chung ,  Chun Lin Tsai ,  Kuo-Ming Wu ,  Shiuan-Jeng Lin ,  Tien Sheng Lin ,  Yi-Min Chen ,  Hung-Chou Lin ,  Yi-Cheng Chiu

IPC: H01L29/06 ,  H01L27/07 ,  H01L21/8234 ,  H01L21/761 ,  H01L29/78 ,  H01L27/06 ,  H01L29/861

Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a bootstrap metal-oxide-semiconductor (MOS) device is integrated with a high voltage metal-oxide-semiconductor (HVMOS) device and a high voltage junction termination (HVJT) device. In some embodiments, a drift well is in the semiconductor substrate. The drift well has a first doping type and has a ring-shaped top layout. A first switching device is on the drift well. A second switching device is on the semiconductor substrate, at an indent in a sidewall the drift well. A peripheral well is in the semiconductor substrate and has a second doping type opposite the first doping type. The peripheral well surrounds the drift well, the first switching device, and the second switching device, and further separates the second switching device from the drift well and the first switching device.

公开(公告)号：US20190131296A1

公开(公告)日：2019-05-02

申请号：US16128578

申请日：2018-09-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Karthick Murukesan ,  Wen-Chih Chiang ,  Chiu-Hua Chung ,  Chun Lin Tsai ,  Kuo-Ming Wu ,  Shiuan-Jeng Lin ,  Tien Sheng Lin ,  Yi-Min Chen ,  Hung-Chou Lin ,  Yi-Cheng Chiu

IPC: H01L27/07 ,  H01L21/8234

Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a bootstrap metal-oxide-semiconductor (MOS) device is integrated with a high voltage metal-oxide-semiconductor (HVMOS) device and a high voltage junction termination (HVJT) device. In some embodiments, a drift well is in the semiconductor substrate. The drift well has a first doping type and has a ring-shaped top layout. A first switching device is on the drift well. A second switching device is on the semiconductor substrate, at an indent in a sidewall the drift well. A peripheral well is in the semiconductor substrate and has a second doping type opposite the first doping type. The peripheral well surrounds the drift well, the first switching device, and the second switching device, and further separates the second switching device from the drift well and the first switching device.

公开(公告)号：US10748986B2

公开(公告)日：2020-08-18

申请号：US15940075

申请日：2018-03-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Guo-Jyun Luo ,  Shiuan-Jeng Lin ,  Chiu-Hua Chung ,  Chen-Chien Chang ,  Han-Zong Pan

IPC: H01L49/02 ,  H01L21/285 ,  H01L27/06 ,  H01L27/08

Abstract: A semiconductor device structure and the formation method thereof are provided. The semiconductor device structure includes a semiconductor substrate and a first capacitor and a second capacitor over the semiconductor substrate. The first capacitor has a first capacitor dielectric layer, and the second capacitor has a second capacitor dielectric layer. The first capacitor dielectric layer is between the second capacitor dielectric layer and the semiconductor substrate. The first capacitor and the second capacitor are electrically connected in parallel. The first capacitor has a first linear temperature coefficient and a first quadratic voltage coefficient. The second capacitor has a second linear temperature coefficient and a second quadratic voltage coefficient. One or both of a first ratio of the first linear temperature coefficient to the second linear temperature coefficient and a second ratio of the first quadratic voltage coefficient to the second quadratic voltage coefficient is negative.