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    PATTERNING A TRANSPARENT WAFER TO FORM AN ALIGNMENT MARK IN THE TRANSPARENT WAFER
    2.
    发明申请
    PATTERNING A TRANSPARENT WAFER TO FORM AN ALIGNMENT MARK IN THE TRANSPARENT WAFER 有权

    公开(公告)号：US20210375780A1

    公开(公告)日：2021-12-02

    申请号：US16884437

    申请日：2020-05-27

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Xin-Hua Huang ,  Ping-Yin Liu

    IPC: H01L23/544 ,  H01L23/00

    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes bonding structure arranged directly between a first substrate and a second substrate. The first substrate includes a first transparent material and a first alignment mark. The first alignment mark is arranged on an outer region of the first substrate and also includes the first transparent material. The first alignment mark is defined by surfaces of the first substrate that are arranged between an uppermost surface of the first substrate and a lowermost surface of the first substrate. The second substrate includes a second alignment mark on an outer region of the second substrate. The second alignment mark directly underlies the first alignment mark, and the bonding structure is arranged directly between the first alignment mark and the second alignment mark.

    Method for alignment, process tool and method for wafer-level alignment
    3.
    发明授权
    Method for alignment, process tool and method for wafer-level alignment 有权

    公开(公告)号：US11189515B2

    公开(公告)日：2021-11-30

    申请号：US16829248

    申请日：2020-03-25

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ching-Hung Wang ,  Ping-Yin Liu ,  Yeong-Jyh Lin ,  Yeur-Luen Tu

    IPC: H01L21/68 ,  G01B11/14 ,  H01L23/544 ,  H01L23/00

    Abstract: Various embodiments of the present application are directed towards a method for workpiece-level alignment with low alignment error and high throughput. In some embodiments, the method comprises aligning a first alignment mark on a first workpiece to a field of view (FOV) of an imaging device based on feedback from the imaging device, and further aligning a second alignment mark on a second workpiece to the first alignment mark based on feedback from the imaging device. The second workpiece is outside the FOV during the aligning of the first alignment mark. The aligning of the second alignment mark is performed without moving the first alignment mark out of the FOV. Further, the imaging device views the second alignment mark, and further views the first alignment mark through the second workpiece, during the aligning of the second alignment mark. The imaging device may, for example, perform imaging with reflected infrared radiation.

    Simultaneous bonding approach for high quality wafer stacking applications
    4.
    发明授权
    Simultaneous bonding approach for high quality wafer stacking applications 有权

    公开(公告)号：US11094575B2

    公开(公告)日：2021-08-17

    申请号：US16429145

    申请日：2019-06-03

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Xin-Hua Huang ,  Ping-Yin Liu ,  Chang-Chen Tsao

    IPC: H01L21/68 ,  H01L21/683 ,  H01L21/18 ,  H01L21/687

    Abstract: In some embodiments, the present disclosure relates to a method for bonding a first wafer to a second wafer. The method includes aligning a first wafer with a second wafer, so the first and second wafers are vertically stacked and have substantially planar profiles extending laterally in parallel. The method further includes bringing the first and second wafers into direct contact with each other at an inter-wafer interface. The bringing of the first and second wafers into direct contact includes deforming the first wafer so that the first wafer has a curved profile and that the inter-wafer interface is localized to a center of the first wafer. The second wafer maintains its substantially planar profile throughout the deforming of the first wafer. The method further includes deforming the first wafer and/or the second wafer to gradually expand the inter-wafer interface from the center to an edge of the first wafer.

    Approach for ultra thin-film transfer and handling
    5.
    发明授权
    Approach for ultra thin-film transfer and handling 有权

    公开(公告)号：US10962878B2

    公开(公告)日：2021-03-30

    申请号：US16666679

    申请日：2019-10-29

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ping-Yin Liu ,  Chang-Ming Wu ,  Chia-Shiung Tsai ,  Xin-Hua Huang

    IPC: G03F7/20 ,  G03F1/64 ,  G03F1/62

    Abstract: A method for forming a pellicle apparatus involves forming a device substrate by depositing one or more pellicle layers defined over a base device layer, where a release layer is formed thereover. An adhesive layer is formed over a transparent carrier substrate. The adhesive layer is bonded to the release layer, defining a composite substrate comprised of the device and carrier substrates. The base device layer is removed from the composite structure and a pellicle frame is attached to an outermost one of the pellicle layers. A pellicle region is isolated from a remainder of the composite structure, and an ablation of the release layer is performed through the transparent carrier substrate, defining the pellicle apparatus comprising a pellicle film attached to the pellicle frame. The pellicle apparatus is then from a remaining portion of the composite substrate.

    SIMULTANEOUS BONDING APPROACH FOR HIGH QUALITY WAFER STACKING APPLICATIONS
    6.
    发明申请
    SIMULTANEOUS BONDING APPROACH FOR HIGH QUALITY WAFER STACKING APPLICATIONS 审中-公开

    公开(公告)号：US20200381283A1

    公开(公告)日：2020-12-03

    申请号：US16429145

    申请日：2019-06-03

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Xin-Hua Huang ,  Ping-Yin Liu ,  Chang-Chen Tsao

    IPC: H01L21/683 ,  H01L21/68 ,  H01L21/687 ,  H01L21/18

    Abstract: In some embodiments, the present disclosure relates to a method for bonding a first wafer to a second wafer. The method includes aligning a first wafer with a second wafer, so the first and second wafers are vertically stacked and have substantially planar profiles extending laterally in parallel. The method further includes bringing the first and second wafers into direct contact with each other at an inter-wafer interface. The bringing of the first and second wafers into direct contact includes deforming the first wafer so that the first wafer has a curved profile and that the inter-wafer interface is localized to a center of the first wafer. The second wafer maintains its substantially planar profile throughout the deforming of the first wafer. The method further includes deforming the first wafer and/or the second wafer to gradually expand the inter-wafer interface from the center to an edge of the first wafer.

    Method for manufacturing a MEMS device by first hybrid bonding a CMOS wafer to a MEMS wafer
    8.
    发明授权
    Method for manufacturing a MEMS device by first hybrid bonding a CMOS wafer to a MEMS wafer 有权

    公开(公告)号：US11279615B2

    公开(公告)日：2022-03-22

    申请号：US16384066

    申请日：2019-04-15

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hung-Hua Lin ,  Chang-Ming Wu ,  Chung-Yi Yu ,  Ping-Yin Liu ,  Jung-Huei Peng

    IPC: B81C1/00 ,  B81B7/00 ,  H01L23/00

    Abstract: A microelectromechanical system (MEMS) structure and method of forming the MEMS device, including forming a first metallization structure over a complementary metal-oxide-semiconductor (CMOS) wafer, where the first metallization structure includes a first sacrificial oxide layer and a first metal contact pad. A second metallization structure is formed over a MEMS wafer, where the second metallization structure includes a second sacrificial oxide layer and a second metal contact pad. The first metallization structure and second metallization structure are then bonded together. After the first metallization structure and second metallization structure are bonded together, patterning and etching the MEMS wafer to form a MEMS element over the second sacrificial oxide layer. After the MEMS element is formed, removing the first sacrificial oxide layer and second sacrificial oxide layer to allow the MEMS element to move freely about an axis.

    Apparatus for bond wave propagation control
    9.
    发明授权
    Apparatus for bond wave propagation control 有权

    公开(公告)号：US11031369B2

    公开(公告)日：2021-06-08

    申请号：US16654377

    申请日：2019-10-16

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Xin-Hua Huang ,  Kuan-Liang Liu ,  Kuo Liang Lu ,  Ping-Yin Liu

    IPC: B23K37/04 ,  H01L23/00 ,  H01L21/683 ,  H01L21/67 ,  H01L21/20 ,  H01L21/762 ,  B23K101/40

    Abstract: An apparatus and method is provided for controlling a propagation of a bond wave during semiconductor processing. The apparatus has a first chuck to selectively retain a first workpiece. A second chuck selectively retains a second workpiece. The first and second chucks selectively secure at least a periphery of the respective first workpiece and second workpiece. An air vacuum is circumferentially located in a region between the first chuck and second chuck. The air vacuum is configured to induce a vacuum between the first workpiece and second workpiece to selectively bring the first workpiece and second workpiece together from a propagation point. The air vacuum can be localized air vacuum guns, a vacuum disk, or an air curtain positioned about the periphery of the region between the first chuck and second chuck. The air curtain induces a lower pressure within the region between the first and second chucks.

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