公开(公告)号：US12009254B2

公开(公告)日：2024-06-11

申请号：US17745127

申请日：2022-05-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yuan Chen ,  Shih-Chuan Chiu ,  Jia-Chuan You ,  Chia-Hao Chang ,  Tien-Lu Lin ,  Yu-Ming Lin

IPC: H01L21/321 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/7684 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/53209

Abstract: A method includes forming a first conductive feature on a substrate, forming a via that contacts the first conductive feature, the via comprising a conductive material, performing a Chemical Mechanical Polishing (CMP) process to a top surface of the via, depositing an Interlayer Dielectric (ILD) layer on the via, forming a trench within the ILD layer to expose the via, and filling the trench with a second conductive feature that contacts the via, the second conductive feature comprising a same material as the conductive material.

公开(公告)号：US20230282720A1

公开(公告)日：2023-09-07

申请号：US18305839

申请日：2023-04-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jia-Chuan You ,  Chia-Hao Chang ,  Tien-Lu Lin ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device according to the present disclosure includes a fin extending from a substrate, a gate structure over a channel region of the fin, a source/drain contact over a source/drain region of the fin, a gate cut feature adjacent the gate structure, a source/drain contact isolation feature adjacent the source/drain contact, a spacer extending along a sidewall of the gate cut feature and a sidewall of the gate structure, a liner extending along a sidewall of the source/drain contact isolation feature and a sidewall of the source/drain contact; and an air gap sandwiched between the spacer and the liner. The gate cut feature and the source/drain contact isolation feature are separated by the spacer, the air gap and the liner.

公开(公告)号：US11532518B2

公开(公告)日：2022-12-20

申请号：US17178762

申请日：2021-02-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu Huang ,  Li-Zhen Yu ,  Sheng-Tsung Wang ,  Jia-Chuan You ,  Chia-Hao Chang ,  Tien-Lu Lin ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L21/8234 ,  H01L21/033 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/308 ,  H01L21/768

Abstract: A method of forming an integrated circuit structure includes forming a first source/drain contact plug over and electrically coupling to a source/drain region of a transistor, forming a first dielectric hard mask overlapping a gate stack, recessing the first source/drain contact plug to form a first recess, forming a second dielectric hard mask in the first recess, recessing an inter-layer dielectric layer to form a second recess, and forming a third dielectric hard mask in the second recess. The third dielectric hard mask contacts both the first dielectric hard mask and the second dielectric hard mask.

公开(公告)号：US11335592B2

公开(公告)日：2022-05-17

申请号：US16573719

申请日：2019-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yuan Chen ,  Shih-Chuan Chiu ,  Jia-Chuan You ,  Chia-Hao Chang ,  Tien-Lu Lin ,  Yu-Ming Lin

IPC: H01L21/768 ,  H01L21/321 ,  H01L23/522 ,  H01L23/532

Abstract: A method includes forming a first conductive feature on a substrate, forming a via that contacts the first conductive feature, the via comprising a conductive material, performing a Chemical Mechanical Polishing (CMP) process to a top surface of the via, depositing an Interlayer Dielectric (ILD) layer on the via, forming a trench within the ILD layer to expose the via, and filling the trench with a second conductive feature that contacts the via, the second conductive feature comprising a same material as the conductive material.

公开(公告)号：US20210313424A1

公开(公告)日：2021-10-07

申请号：US17352682

申请日：2021-06-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Chuan Chiu ,  Chia-Hao Chang ,  Jia-Chuan You ,  Tien-Lu Lin ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L29/08 ,  H01L21/768 ,  H01L29/78 ,  H01L29/66

Abstract: A semiconductor device comprises a fin disposed on a substrate, a source/drain feature disposed over the fin, a silicide layer disposed over the source/drain feature, a seed metal layer disposed over the silicide layer and wrapping around the source/drain feature, and a metal layer disposed on the silicide layer, where the metal layer contacts the seed metal layer.

公开(公告)号：US11107925B2

公开(公告)日：2021-08-31

申请号：US16514736

申请日：2019-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen Yu ,  Jia-Chuan You ,  Chia-Hao Chang ,  Tien-Lu Lin ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L21/02 ,  H01L29/78 ,  H01L27/088 ,  H01L29/66

Abstract: A method includes providing a semiconductor structure having metal gate structures (MGs), gate spacers disposed on sidewalls of the MGs, and source/drain (S/D) features disposed adjacent to the gate spacers; forming a first dielectric layer over the MGs and forming S/D contacts (MDs) over the S/D features; forming a second dielectric layer over the first dielectric layer, where portions of the second dielectric layer contact the MDs and the second dielectric layer is different from the first dielectric layer in composition; removing the portions of the second dielectric layer that contact the MDs; forming a conductive layer over the MDs and over the first dielectric layer; and removing portions of the conductive layer to form conductive features over the MDs.

公开(公告)号：US11043558B2

公开(公告)日：2021-06-22

申请号：US16556922

申请日：2019-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Chuan Chiu ,  Chia-Hao Chang ,  Jia-Chuan You ,  Tien-Lu Lin ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L21/768 ,  H01L29/66 ,  H01L29/08 ,  H01L29/78

Abstract: The present disclosure provides a method for semiconductor fabrication. The method includes epitaxially growing source/drain feature on a fin; forming a silicide layer over the epitaxial source/drain feature; forming a seed metal layer on the silicide layer; forming a contact metal layer over the seed metal layer using a bottom-up growth approach; and depositing a fill metal layer over the contact metal layer.

公开(公告)号：US10964559B2

公开(公告)日：2021-03-30

申请号：US14320181

申请日：2014-06-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tai-I Yang ,  Chih-Shen Yang ,  Tien-Lu Lin

IPC: H01L21/67 ,  H01L21/311

Abstract: A wafer etching apparatus and a method for controlling an etch bath of a wafer is provided. The wafer etching apparatus includes an etching tank comprising an etch bath, an etch bath recycle system connected to the etching tank, a real time monitor (RTM) system connected to the etching tank, and a control system coupled with the RTM system and the etch bath recycle system. The wafer etching apparatus and the method for controlling an etch bath of the wafer both control the silicate concentration in the etch bath to stable an etching selectivity with respect to silicon oxide and silicon nitride.

公开(公告)号：US20190244897A1

公开(公告)日：2019-08-08

申请号：US16384027

申请日：2019-04-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Wei Liu ,  Tai-I Yang ,  Cheng-Chi Chuang ,  Tien-Lu Lin

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a dielectric structure over a substrate, and a first interconnect structure arranged within the dielectric structure. A lower interconnect structure is arranged within the dielectric structure. The first interconnect structure and the lower interconnect structure comprise one or more different conductive materials. The first interconnect structure continuously extends from directly over a topmost surface of the lower interconnect structure facing away from the substrate to along opposing outer sidewalls of the lower interconnect structure.

公开(公告)号：US10002826B2

公开(公告)日：2018-06-19

申请号：US14524228

申请日：2014-10-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Tai-I Yang ,  Yu-Chieh Liao ,  Tien-Lu Lin ,  Tien-I Bao

IPC: H01L29/76 ,  H01L23/522 ,  H01L23/485 ,  H01L29/417 ,  H01L29/78 ,  H01L21/768 ,  H01L23/532 ,  H01L29/66

CPC classification number: H01L23/5226 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76879 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53228 ,  H01L23/53257 ,  H01L29/41758 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a first dielectric layer over the semiconductor substrate. The semiconductor device structure includes a first conductive line embedded in the first dielectric layer. The semiconductor device structure includes a second dielectric layer over the first dielectric layer and the first conductive line. The semiconductor device structure includes a second conductive line over the second dielectric layer. The second dielectric layer is between the first conductive line and the second conductive line. The semiconductor device structure includes conductive pillars passing through the second dielectric layer to electrically connect the first conductive line to the second conductive line. The conductive pillars are spaced apart from each other.