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公开(公告)号：US20230253256A1
公开(公告)日：2023-08-10
申请号：US18303173
申请日：2023-04-19
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Wen-Hung Huang , Kuo-Feng Yu , Jian-Hao Chen , Shan-Mei Liao , Jer-Fu Wang , Yung-Hsiang Chan
IPC: H01L21/8234 , H01L29/51 , H01L27/088 , H01L21/28
CPC classification number: H01L21/823462 , H01L29/517 , H01L27/0886 , H01L21/28185
Abstract: A method includes forming a first gate dielectric, a second gate dielectric, and a third gate dielectric over a first semiconductor region, a second semiconductor region, and a third semiconductor region, respectively. The method further includes depositing a first lanthanum-containing layer overlapping the first gate dielectric, and depositing a second lanthanum-containing layer overlapping the second gate dielectric. The second lanthanum-containing layer is thinner than the first lanthanum-containing layer. An anneal process is then performed to drive lanthanum in the first lanthanum-containing layer and the second lanthanum-containing layer into the first gate dielectric and the second gate dielectric, respectively. During the anneal process, the third gate dielectric is free from lanthanum-containing layers thereon.
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公开(公告)号：US20210257258A1
公开(公告)日：2021-08-19
申请号：US16939610
申请日：2020-07-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Wen-Hung Huang , Kuo-Feng Yu , Jian-Hao Chen , Shan-Mei Liao , Jer-Fu Wang , Yung-Hsiang Chan
IPC: H01L21/8234 , H01L21/28 , H01L27/088 , H01L29/51
Abstract: A method includes forming a first gate dielectric, a second gate dielectric, and a third gate dielectric over a first semiconductor region, a second semiconductor region, and a third semiconductor region, respectively. The method further includes depositing a first lanthanum-containing layer overlapping the first gate dielectric, and depositing a second lanthanum-containing layer overlapping the second gate dielectric. The second lanthanum-containing layer is thinner than the first lanthanum-containing layer. An anneal process is then performed to drive lanthanum in the first lanthanum-containing layer and the second lanthanum-containing layer into the first gate dielectric and the second gate dielectric, respectively. During the anneal process, the third gate dielectric is free from lanthanum-containing layers thereon.
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公开(公告)号：US09965409B2
公开(公告)日：2018-05-08
申请号：US15461737
申请日：2017-03-17
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Ying-Yu Hsu , Chien-Chun Tsai , Wen-Hung Huang
CPC classification number: G06F13/1689 , G06F1/12 , G06F11/1604 , G06F11/1679 , G06F12/0246
Abstract: The present disclosure relates to a system which includes a memory controller interface, a memory unit interface, and a correction block. The memory controller interface includes a digitally-controlled delay line (DCDL). The memory unit interface is coupled to the memory controller interface, and is configured to communicate with the memory controller interface through a first signal and a second signal. The correction block is configured to determine a result of alignment between the first signal and the second signal, and to provide a correction signal configured to align the first signal to the second signal. Other systems, devices and methods are disclosed.
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公开(公告)号：US12034572B2
公开(公告)日：2024-07-09
申请号：US18133976
申请日：2023-04-12
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shu-Chun Yang , Wen-Hung Huang
CPC classification number: H04L25/03057 , H04L25/0212
Abstract: An apparatus and method for providing a decision feedback equalizer are disclosed herein. In some embodiments, a method and apparatus for reduction of inter-symbol interference (ISI) caused by communication channel impairments is disclosed. In some embodiments, a decision feedback equalizer includes a plurality of delay latches connected in series, a slicer circuit configured to receive an input signal from a communication channel and delayed feedback signals from the plurality of delay latches and determine a logical state of the received input signal, wherein the slicer circuit further comprises a dynamic threshold voltage calibration circuit configured to regulate a current flow between output nodes of the slicer circuit and ground based on the received delayed feedback signal and impulse response coefficients of the communication channel.
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公开(公告)号：US09619409B2
公开(公告)日：2017-04-11
申请号：US13736195
申请日：2013-01-08
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Ying-Yu Hsu , Chien-Chun Tsai , Wen-Hung Huang
CPC classification number: G06F13/1689 , G06F1/12 , G06F11/1604 , G06F11/1679 , G06F12/0246
Abstract: The present disclosure relates to an interface comprising a memory controller and a memory unit coupled to the memory controller and configured to communicate with the memory controller through a first signal and a second signal. The interface further comprises a determination unit comprising judgment logic configured to send a control signal configured to align the first signal with the second signal. The memory controller further comprises a digitally-controlled delay line (DCDL) coupled to the determination unit and configured to receive the control signal, wherein the determination unit instructs the DCDL to adjust a delay of the first signal to align the first signal with the second signal. The memory controller further comprises a value register configured to store a signal delay value corresponding to alignment between the first signal with the second signal which is contained within the control signal. Other devices and methods are disclosed.
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Patent Agency Ranking
公开(公告)号：US09267988B2
公开(公告)日：2016-02-23
申请号：US13892334
申请日：2013-05-13
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Wen-Hung Huang , Chien-Chun Tsai , Ying-Yu Hsu
IPC: G01R31/317
CPC classification number: G01R31/31708 , G01R31/31711
Abstract: An eye diagram capture device includes a delay line arranged to receive a digital signal and output time delayed version of the digital signal. An edge detection circuit is arranged to receive the digital signal and the time delayed version of the digital signal, the edge detection circuit operating to output a signal corresponding to a logical value of the digital signal received coincident with an edge of the time delay version of the digital signal. A voltage comparator is arranged to receive the digital signal and a reference voltage. The voltage comparator operates to output a first signal when the a voltage of the digital signal and the reference voltage are equal to each other.
Abstract translation: 眼图捕获装置包括布置成接收数字信号并输出数字信号的时间延迟版本的延迟线。 边缘检测电路被布置为接收数字信号和数字信号的时间延迟版本，边缘检测电路操作以输出与所接收的数字信号的逻辑值相对应的信号，其与时间延迟版本 数字信号。 电压比较器布置成接收数字信号和参考电压。 当数字信号的电压和参考电压彼此相等时，电压比较器操作以输出第一信号。
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公开(公告)号：US20230327921A1
公开(公告)日：2023-10-12
申请号：US18133976
申请日：2023-04-12
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shu-Chun YANG , Wen-Hung Huang
CPC classification number: H04L25/03057 , H04L25/0212
Abstract: An apparatus and method for providing a decision feedback equalizer are disclosed herein. In some embodiments, a method and apparatus for reduction of inter-symbol interference (ISI) caused by communication channel impairments is disclosed. In some embodiments, a decision feedback equalizer includes a plurality of delay latches connected in series, a slicer circuit configured to receive an input signal from a communication channel and delayed feedback signals from the plurality of delay latches and determine a logical state of the received input signal, wherein the slicer circuit further comprises a dynamic threshold voltage calibration circuit configured to regulate a current flow between output nodes of the slicer circuit and ground based on the received delayed feedback signal and impulse response coefficients of the communication channel.
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公开(公告)号：US20230163129A1
公开(公告)日：2023-05-25
申请号：US17703329
申请日：2022-03-24
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hsueh-Ju Chen , Yi Hsuan Chen , Jyun-Yi Wu , Wen-Hung Huang , Tsung-Da Lin , Jian-Hao Chen , Cheng-Lung Hung , Kuo-Feng Yu
IPC: H01L27/092 , H01L29/10 , H01L29/78 , H01L29/66 , H01L21/8238
CPC classification number: H01L27/0922 , H01L27/0924 , H01L29/1037 , H01L29/7851 , H01L29/66818 , H01L21/823807 , H01L21/823821
Abstract: In an embodiment, a device includes: an isolation region on a substrate; a first semiconductor fin protruding above the isolation region; a first gate dielectric on a first channel region of the first semiconductor fin, the first gate dielectric including a first interfacial layer and a first high-k dielectric layer; a second semiconductor fin protruding above the isolation region; and a second gate dielectric on a second channel region of the second semiconductor fin, the second gate dielectric including a second interfacial layer and a second high-k dielectric layer, a first portion of the first interfacial layer on the first channel region having a greater thickness than a second portion of the second interfacial layer on the second channel region, the second channel region having a greater height than the first channel region.
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公开(公告)号：US20170192913A1
公开(公告)日：2017-07-06
申请号：US15461737
申请日：2017-03-17
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Ying-Yu Hsu , Chien-Chun Tsai , Wen-Hung Huang
CPC classification number: G06F13/1689 , G06F1/12 , G06F11/1604 , G06F11/1679 , G06F12/0246
Abstract: The present disclosure relates to a system which includes a memory controller interface, a memory unit interface, and a correction block. The memory controller interface includes a digitally-controlled delay line (DCDL). The memory unit interface is coupled to the memory controller interface, and is configured to communicate with the memory controller interface through a first signal and a second signal. The correction block is configured to determine a result of alignment between the first signal and the second signal, and to provide a correction signal configured to align the first signal to the second signal. Other systems, devices and methods are disclosed.
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公开(公告)号：US09379719B1
公开(公告)日：2016-06-28
申请号：US14674579
申请日：2015-03-31
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Wen-Hung Huang
CPC classification number: H03L7/085 , H03L2207/50
Abstract: A device is disclosed that includes a control module and a gain estimation module. The control module is configured to superimpose two non-zero values on a frequency control word to respectively generate a first and a second modified fractional reference phase signals, under a condition that a fractional part of the frequency control word is smaller than a predetermined value. The gain estimation module is configured to calculate a first and a second estimated gain values respectively based on the first and the second modified fractional reference phase signals. The control module is further configured to calculate an estimated digital-to-time converter gain value based on an interpolation of the first and the second estimated gain values.
Abstract translation: 公开了一种包括控制模块和增益估计模块的装置。 控制模块被配置为在频率控制字的小数部分小于预定值的条件下，在频率控制字上叠加两个非零值以分别产生第一和第二修改的分数参考相位信号。 增益估计模块被配置为分别基于第一和第二修改的分数基准相位信号来计算第一和第二估计增益值。 控制模块还被配置为基于第一和第二估计增益值的内插来计算估计的数字 - 时间转换器增益值。
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