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    Static semiconductor memory device driving bit line potential by bipolar transistor shared by adjacent memory cells
    1.
    发明授权
    Static semiconductor memory device driving bit line potential by bipolar transistor shared by adjacent memory cells 失效
    静态半导体存储器件通过由相邻存储器单元共享的双极晶体管驱动位线电位

    公开(公告)号：US5966324A

    公开(公告)日：1999-10-12

    申请号：US896333

    申请日：1997-07-17

    申请人： Tomohisa Wada ,  Yutaka Arita

    发明人： Tomohisa Wada ,  Yutaka Arita

    IPC分类号： G11C11/411 ,  G11C11/412 ,  H01L27/10 ,  H01L27/11 ,  G11C11/34

    CPC分类号： H01L27/1112 ,  G11C11/412

    摘要： Memory cells which are adjacent to each other along a column direction share a bipolar transistor driving the potential level of a corresponding bit line. Other memory cells which are adjacent to each other in the column direction share another bipolar transistor driving the potential level of another corresponding bit line. Each bipolar transistor drives the potential level of the corresponding bit line in response to storage information of a selected memory cell, whereby data can be read at a high speed with a low power supply voltage.

    摘要翻译： 沿着列方向彼此相邻的存储单元共享驱动相应位线的电位的双极晶体管。 在列方向上彼此相邻的其他存储单元共享驱动另一对应位线的电位电平的另一双极晶体管。 每个双极晶体管响应于所选择的存储单元的存储信息驱动相应位线的电位电平，由此可以以低电源电压高速读取数据。

    Semiconductor memory device having strobe buffer and output buffer
    2.
    发明授权
    Semiconductor memory device having strobe buffer and output buffer 有权
    具有选通缓冲器和输出缓冲器的半导体存储器件

    公开(公告)号：US6021081A

    公开(公告)日：2000-02-01

    申请号：US195461

    申请日：1998-11-18

    申请人： Yoshiko Higashide ,  Tomohisa Wada ,  Yutaka Arita

    发明人： Yoshiko Higashide ,  Tomohisa Wada ,  Yutaka Arita

    IPC分类号： G11C11/413 ,  G11C7/10 ,  G11C11/417 ,  G11C11/419 ,  H01L21/8244 ,  H01L27/10 ,  H01L27/11 ,  G11C7/00

    CPC分类号： G11C7/1051 ,  G11C11/419

    摘要： An output buffer is connected to a first power supply line and a first ground line, and a strobe buffer is connected to a second power supply line and a second ground line. The first power supply line is connected to a first pad, the first ground line is connected to a second pad, the second power supply line is connected to a third pad, and the second ground line is connected to a fourth pad, respectively. The first and second power supply lines are not connected inside the chip, and the first and second ground lines are not connected inside the chip. The first and third pads are separately connected to the respective lead terminals, and the second and fourth pads are separately connected to the respective lead terminals.

    摘要翻译： 输出缓冲器连接到第一电源线和第一接地线，并且选通缓冲器连接到第二电源线和第二接地线。 第一电源线连接到第一焊盘，第一接地线连接到第二焊盘，第二电源线连接到第三焊盘，第二接地线分别连接到第四焊盘。 第一和第二电源线未连接在芯片内部，并且第一和第二接地线未连接在芯片内部。 第一和第三焊盘分别连接到相应的引线端子，第二和第四焊盘分别连接到相应的引线端子。

    Semiconductor memory device having on-chip test circuit and operating method thereof
    3.
    发明授权
    Semiconductor memory device having on-chip test circuit and operating method thereof 失效
    具有片上测试电路的半导体存储器件及其工作方法

    公开(公告)号：US5132937A

    公开(公告)日：1992-07-21

    申请号：US527205

    申请日：1990-05-23

    申请人： Nobuhiro Tuda ,  Yutaka Arita

    发明人： Nobuhiro Tuda ,  Yutaka Arita

    IPC分类号： G11C29/00 ,  G11C11/401 ,  G11C29/12 ,  G11C29/24 ,  G11C29/34 ,  G11C29/44

    CPC分类号： G11C29/44 ,  G11C29/24

    摘要： Same test data is written into corresponding memory cells of each subarray of a memory cell array to be read out. A comparing and determining circuit determines whether the data read out from each memory cell has the same logic or not, and the data proves defective when any one of the data has different logic. An output of the comparing and determining circuit is stored in a register to be externally outputted through a predetermined pin (e.g. output enable pin). Timing in which the register accepts the data stored in the comparing and determining circuit is controlled by a switching controlling signal generating circuit disposed in a semiconductor memory device. As the above, all signals necessary for a test are generated in the semiconductor memory device, and the test result is outputted through an existing pin, so that it is structured by the same number of pins as that of a standard semiconductor memory device without a testing function.

    摘要翻译： 将相同的测试数据写入要读出的存储单元阵列的每个子阵列的相应存储单元中。 比较和确定电路确定从每个存储单元读出的数据是否具有相同的逻辑，并且当数据中的任何一个具有不同的逻辑时，数据证明是有缺陷的。 比较和确定电路的输出被存储在寄存器中，以通过预定的引脚（例如，输出使能引脚）从外部输出。 寄存器接受存储在比较和确定电路中的数据的定时由设置在半导体存储器件中的开关控制信号发生电路控制。 如上所述，在半导体存储器件中产生测试所需的所有信号，并且通过现有的引脚输出测试结果，使得其由与没有标准半导体存储器件的标准半导体存储器件相同数量的引脚构成 测试功能。

    Output buffer semiconductor and method for controlling current flow in an output switching device
    4.
    发明授权
    Output buffer semiconductor and method for controlling current flow in an output switching device 失效
    输出缓冲半导体以及用于控制输出开关器件中的电流的方法

    公开(公告)号：US4985644A

    公开(公告)日：1991-01-15

    申请号：US274438

    申请日：1988-11-22

    申请人： Yoshihiko Okihara ,  Yutaka Arita

    发明人： Yoshihiko Okihara ,  Yutaka Arita

    IPC分类号： G05F1/56 ,  G11C11/409 ,  G11C11/417 ,  H03K19/003 ,  H03K19/094

    CPC分类号： H03K19/09429 ,  H03K19/00361

    摘要： An output buffer circuit comprises a NAND circuit and a NOR circuit each receiving an output a of a signal source and an output b of an output control circuit and an output driving circuit formed by a p channel MOS transistor and an n channel MOS transistor receiving outputs of the NAND circuit and the NOR circuit. Large output capacitance is connected to an output of the output driving circuit. The n channel MOS transistor is connected between the output of the NOR circuit and a ground potential, and has its gate receiving the output of the output driving circuit. When the output of the output driving circuit is at an "H" level, the rise of the output of the NOR circuit is controlled, so that the output of the output driving circuit is first changed to the "L" level slowly. Therefore, discharge current from the output capacitance rises slowly. However, since transconductance of the n channel MOS transistor in the output driving circuit is set large, the output of the output driving circuit falls rapidly from halfway.

    摘要翻译： 一个输出缓冲电路包括一个NAND电路和一个NOR电路，每一个都接收一个信号源的输出a和一个输出控制电路的输出b和一个由p沟道MOS晶体管和n沟道MOS晶体管形成的输出驱动电路， NAND电路和NOR电路。 大输出电容连接到输出驱动电路的输出。 n沟道MOS晶体管连接在NOR电路的输出端和地电位之间，并且其栅极接收输出驱动电路的输出。 当输出驱动电路的输出为“H”电平时，NOR电路的输出的上升被控制，使输出驱动电路的输出缓慢地变为“L”电平。 因此，来自输出电容的放电电流缓慢上升。 然而，由于输出驱动电路中的n沟道MOS晶体管的跨导被设定得较大，所以输出驱动电路的输出从一半急剧下降。

    Semiconductor memory device adapted for preventing a test mode operation from undesirably occurring
    6.
    发明授权
    Semiconductor memory device adapted for preventing a test mode operation from undesirably occurring 失效
    适于防止测试模式操作不期望地发生的半导体存储器件

    公开(公告)号：US5384741A

    公开(公告)日：1995-01-24

    申请号：US186955

    申请日：1994-01-27

    申请人： Yoshiyuki Haraguchi ,  Yutaka Arita

    发明人： Yoshiyuki Haraguchi ,  Yutaka Arita

    IPC分类号： G01R31/28 ,  G11C11/401 ,  G11C11/413 ,  G11C29/00 ,  G11C29/14 ,  G11C29/46 ,  H01L21/66 ,  H01L27/10

    CPC分类号： G11C29/46

    摘要： A semiconductor memory device having a circuit for preventing the operation of a test mode includes a first terminal for receiving an externally applied high voltage exceeding a power supply potential, a second terminal for receiving an externally applied test mode signal and a high voltage detector for detecting that a high voltage signal has been applied through the first terminal. A test mode signal holding circuit is responsive to the high voltage detector and holds the test mode signal applied through the second terminal. A test circuit is responsive to the test mode signal held in the test mode signal holding circuit and performs a test in the semiconductor memory device. A disabling circuit is provided to disable the high voltage detector.

    摘要翻译： 具有用于防止测试模式操作的电路的半导体存储器件包括用于接收外部施加的超过电源电位的高电压的第一端子，用于接收外部施加的测试模式信号的第二端子和用于检测的高电压检测器 已经通过第一端子施加高电压信号。 测试模式信号保持电路响应于高电压检测器并保持通过第二端子施加的测试模式信号。 测试电路响应于保持在测试模式信号保持电路中的测试模式信号，并在半导体存储器件中进行测试。 提供禁用电路以禁用高电压检测器。

    Bit line equalize circuit of semiconductor memory device
    7.
    发明授权
    Bit line equalize circuit of semiconductor memory device 失效
    半导体存储器件的位线均衡电路

    公开(公告)号：US5946251A

    公开(公告)日：1999-08-31

    申请号：US10037

    申请日：1998-01-21

    申请人： Hirotoshi Sato ,  Yutaka Arita

    发明人： Hirotoshi Sato ,  Yutaka Arita

    IPC分类号： G11C11/41 ,  G11C7/12 ,  G11C11/414 ,  G11C11/419 ,  G11C11/40

    CPC分类号： G11C11/419 ,  G11C7/12

    摘要： A memory cell data is read/written to a memory cell by utilizing the base current of a bipolar transistor having its emitter coupled to a bit line. When activated, a bit line precharge circuit precharges the bit line to a level of a built-in voltage between the emitter and the base of the memory cell bipolar transistor. When bit lines in a pair are lowered in potential from the H level to the L level, the base electrode node potential of the bipolar transistor is never changed to a negative potential by capacitance coupling, and conduction of an access transistor and destruction of memory cell data are prevented. A semiconductor memory device is implemented which does not cause data destruction and can stably operate at high speed even under a low power supply voltage.

    摘要翻译： 通过利用其发射极耦合到位线的双极晶体管的基极电流将存储单元数据读取/写入存储单元。 当被激活时，位线预充电电路将位线预充电到存储单元双极晶体管的发射极和基极之间的内置电压的电平。 当一对中的位线从H电平降低到L电平时，双极晶体管的基极节点电位从不通过电容耦合变为负电位，并且存取晶体管的导通和存储单元的破坏 数据被阻止。 实现半导体存储器件，其不会导致数据破坏，并且即使在低电源电压下也能够以高速稳定地操作。

    Static type semiconductor memory device with two word lines for one row
    8.
    发明授权
    Static type semiconductor memory device with two word lines for one row 失效
    静态型半导体存储器件，两行字线一行

    公开(公告)号：US5764565A

    公开(公告)日：1998-06-09

    申请号：US874636

    申请日：1997-06-13

    申请人： Hirotoshi Sato ,  Motomu Ukita ,  Yutaka Arita

    发明人： Hirotoshi Sato ,  Motomu Ukita ,  Yutaka Arita

    IPC分类号： G11C11/412 ,  G11C11/41 ,  G11C11/411 ,  G11C11/413 ,  G11C11/00

    CPC分类号： G11C11/413 ,  G11C11/41

    摘要： A memory cell includes two bipolar transistors. An upper side word line is connected to the gates of one access transistor and one depletion type transistor in the memory cell. A lower side word line is connected to the gates of the other access transistor and the other depletion type transistor in the memory cell. In data write operation, the potential on the upper side word line is set to "H" level for a prescribed period and the potential on the lower side word line is thereafter set to "H" level for a prescribed period, regardless of the type of data. As a result, a circuit related to row decoding can be simplified since a circuit for determining the type of data is not necessary in the circuit related to row decoding.

    摘要翻译： 存储单元包括两个双极晶体管。 上侧字线连接到存储单元中的一个存取晶体管和一个耗尽型晶体管的栅极。 下侧字线连接到存储单元中的另一个存取晶体管和另一个耗尽型晶体管的栅极。 在数据写入操作中，将上侧字线的电位设定为“H”电平达规定时间段，然后将下侧字线的电位设定为“H”电平达规定期间，而不管其类型如何 数据的。 结果，由于在与行解码相关的电路中不需要用于确定数据类型的电路，因此可以简化与行解码有关的电路。

    Semiconductor memory device adapted for preventing a test mode operation from undesirably occurring
    9.
    发明授权
    Semiconductor memory device adapted for preventing a test mode operation from undesirably occurring 失效
    适于防止测试模式操作不期望地发生的半导体存储器件

    公开(公告)号：US5305267A

    公开(公告)日：1994-04-19

    申请号：US51405

    申请日：1993-04-23

    申请人： Yoshiyuki Haraguchi ,  Yutaka Arita

    发明人： Yoshiyuki Haraguchi ,  Yutaka Arita

    IPC分类号： G01R31/28 ,  G11C11/401 ,  G11C11/413 ,  G11C29/00 ,  G11C29/14 ,  G11C29/46 ,  H01L21/66 ,  H01L27/10

    CPC分类号： G11C29/46

    摘要： When a pre-shipment test of a SRAM is requested, a pulse signal PL having a pulse width exceeding a predetermined time length is applied through a terminal 62. A pulse width detecting circuit 80 detects the pulse width of the applied pulse signal to provide a holding signal HD. A test mode signal holding circuit 90 holds an externally applied test mode request signal TM' in response to the holding signal HD. After the completion of the pre-shipment test, pulse width detecting circuit 80 is disabled by a fusion of a fuse 71. Fuse 71 is fused after the pre-shipment test is conducted, whereby the test mode operation is prevented from undesirably occurring.

    摘要翻译： 当请求SRAM的装运前测试时，通过端子62施加脉冲宽度超过预定时间长度的脉冲信号PL。脉冲宽度检测电路80检测施加的脉冲信号的脉冲宽度以提供 保持信号HD。 测试模式信号保持电路90响应于保持信号HD保持外部施加的测试模式请求信号TM'。 在装运前测试完成之后，脉冲宽度检测电路80被保险丝熔断器71禁用。在进行装运前测试之后，保险丝71熔断，从而防止测试模式操作不期望地发生。