公开(公告)号：US20170221913A1

公开(公告)日：2017-08-03

申请号：US15487419

申请日：2017-04-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ching Hsu ,  Ko-Chi Chen ,  Shen-De Wang

IPC: H01L27/11529 ,  H01L27/11531

CPC classification number: H01L27/11529 ,  H01L27/11524 ,  H01L27/11531 ,  H01L27/11536 ,  H01L27/11539 ,  H01L27/11573

Abstract: A method of fabricating a semiconductor device includes providing a substrate with a memory region and a logic region, forming a recess of the substrate in the memory region, forming a non-volatile gate stack in the recess, and forming a logic gate stack in the logic region after forming the non-volatile gate stack.

公开(公告)号：US20170221911A1

公开(公告)日：2017-08-03

申请号：US15081946

申请日：2016-03-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  Ko-Chi Chen ,  Shen-De Wang

IPC: H01L27/115 ,  G11C16/14 ,  H01L21/28 ,  G11C16/10 ,  H01L21/3205 ,  H01L29/66 ,  H01L29/423 ,  H01L29/788 ,  G11C16/04 ,  H01L21/311

CPC classification number: H01L29/40114 ,  G11C16/0408 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32055 ,  H01L27/11524 ,  H01L27/11534 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7883

Abstract: The flash memory includes a stacked gate disposed on a substrate. The stacked gate includes an erase gate and two floating gates. Each floating gate has an acute angle pointing toward the erase gate. There is a high electric field formed around the acute angle so that the flash memory can perform an erase mode even at a lower operational voltage. Furthermore, the flash memory does not use any control gate to perform a write mode.

公开(公告)号：US12272397B2

公开(公告)日：2025-04-08

申请号：US18180864

申请日：2023-03-09

Applicant: United Microelectronics Corp.

Inventor： Yi Ting Hung ,  Ko-Chi Chen ,  Tzu-Yun Chang

IPC: G11C11/00 ,  G11C13/00

Abstract: A forming operation method of a resistive random access memory is provided. The method includes the following steps. A positive pulse and a negative pulse are sequentially applied, by a bit line/source line driver, to multiple resistive random access memory cells in a direction form a farthest location to a nearest location based on the bit line/source line driver through a bit line and a source line to break down a dielectric film of each of the resistive random access memory cells and generate a conductive filament of each of the resistive random access memory cells.

公开(公告)号：US20240282371A1

公开(公告)日：2024-08-22

申请号：US18180864

申请日：2023-03-09

Applicant: United Microelectronics Corp.

Inventor： Yi Ting Hung ,  Ko-Chi Chen ,  Tzu-Yun Chang

IPC: G11C13/00

CPC classification number: G11C13/0026 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/004 ,  G11C2013/0045

Abstract: A forming operation method of a resistive random access memory is provided. The method includes the following steps. A positive pulse and a negative pulse are sequentially applied, by a bit line/source line driver, to multiple resistive random access memory cells in a direction form a farthest location to a nearest location based on the bit line/source line driver through a bit line and a source line to break down a dielectric film of each of the resistive random access memory cells and generate a conductive filament of each of the resistive random access memory cells.

公开(公告)号：US20220293679A1

公开(公告)日：2022-09-15

申请号：US17224140

申请日：2021-04-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Hsin Hsu ,  Ko-Chi Chen ,  Tzu-Yun Chang ,  Chung-Tse Chen

IPC: H01L27/24 ,  H01L45/00

Abstract: A semiconductor memory device includes a substrate, a dielectric layer on the substrate, and a contact plug in the dielectric layer. An upper portion of the contact plug protrudes from a top surface of the dielectric layer. The upper portion of the contact plug acts as a first electrode. A buffer layer is disposed on the dielectric layer and beside the upper portion of the contact plug. A resistive-switching layer is disposed beside the buffer layer. A second electrode is disposed beside the resistive-switching layer.

公开(公告)号：US09761680B2

公开(公告)日：2017-09-12

申请号：US14923409

申请日：2015-10-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Dongdong Li ,  Ko-Chi Chen ,  Shen-De Wang

IPC: H01L29/788 ,  H01L29/423 ,  H01L27/11534 ,  H01L29/66

CPC classification number: H01L29/42328 ,  H01L27/11534 ,  H01L29/42336 ,  H01L29/66825

Abstract: The present invention provides a semiconductor device, including a substrate with a memory region and a logic region, the substrate having a recess disposed in the memory region, a logic gate stack disposed in the logic region, and a non-volatile memory disposed in the recess. The non-volatile memory includes at least two floating gates and at least two control gates disposed on the floating gates, where each floating gate has a step-shaped bottom, and the step-shaped bottom includes a first bottom surface and a second bottom surface lower than the first bottom surface.

公开(公告)号：US20170084622A1

公开(公告)日：2017-03-23

申请号：US14856577

申请日：2015-09-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ching Hsu ,  Ko-Chi Chen ,  Shen-De Wang

IPC: H01L27/115

CPC classification number: H01L27/11529 ,  H01L27/11524 ,  H01L27/11531 ,  H01L27/11536 ,  H01L27/11539 ,  H01L27/11573

Abstract: A semiconductor device includes a substrate with a memory region and a logic region, a logic gate stack, and a non-volatile gate stack. The substrate has a recess disposed in the memory region. The logic gate stack is disposed in the logic region and has a first top surface. The non-volatile gate stack is disposed in the recess and has a second top surface. The second top surface is lower than the first top surface by a step height.

公开(公告)号：US11706933B2

公开(公告)日：2023-07-18

申请号：US17224140

申请日：2021-04-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Hsin Hsu ,  Ko-Chi Chen ,  Tzu-Yun Chang ,  Chung-Tse Chen

IPC: H10B63/00 ,  H10N70/20 ,  H10N70/00

CPC classification number: H10B63/80 ,  H10B63/30 ,  H10N70/041 ,  H10N70/24 ,  H10N70/8833

Abstract: A semiconductor memory device includes a substrate, a dielectric layer on the substrate, and a contact plug in the dielectric layer. An upper portion of the contact plug protrudes from a top surface of the dielectric layer. The upper portion of the contact plug acts as a first electrode. A buffer layer is disposed on the dielectric layer and beside the upper portion of the contact plug. A resistive-switching layer is disposed beside the buffer layer. A second electrode is disposed beside the resistive-switching layer.

公开(公告)号：US10074692B2

公开(公告)日：2018-09-11

申请号：US15884827

申请日：2018-01-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Hsin Hsu ,  Ko-Chi Chen ,  Tzu-Yun Chang

IPC: H01L45/00 ,  H01L27/24 ,  H01L23/528

CPC classification number: H01L27/2463 ,  H01L23/528 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16 ,  H01L45/1608 ,  H05K999/99

Abstract: A semiconductor structure includes a memory unit structure. The memory unit structure includes a transistor, a first electrode, two second electrode, and two resistive random access memory (RRAM) elements. The first electrode and the two second electrodes are disposed in a horizontal plane. The first electrode is disposed between the two second electrodes. The first electrode and the two second electrodes are disposed in parallel. The first electrode is coupled to a source region of the transistor. One of the two RRAM elements is disposed between the first electrode and one of the two second electrodes. The other one of the two RRAM elements is disposed between the first electrode and the other one of the two second electrodes.

公开(公告)号：US09978762B2

公开(公告)日：2018-05-22

申请号：US15487419

申请日：2017-04-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ching Hsu ,  Ko-Chi Chen ,  Shen-De Wang

IPC: H01L27/11531 ,  H01L27/11529 ,  H01L27/11573

CPC classification number: H01L27/11529 ,  H01L27/11524 ,  H01L27/11531 ,  H01L27/11536 ,  H01L27/11539 ,  H01L27/11573

Abstract: A method of fabricating a semiconductor device includes providing a substrate with a memory region and a logic region, forming a recess of the substrate in the memory region, forming a non-volatile gate stack in the recess, and forming a logic gate stack in the logic region after forming the non-volatile gate stack.