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    TESTKEY STRUCTURE AND METHOD OF MEASURING DEVICE DEFECT OR CONNECTION DEFECT BY USING THE SAME
    1.
    发明申请
    TESTKEY STRUCTURE AND METHOD OF MEASURING DEVICE DEFECT OR CONNECTION DEFECT BY USING THE SAME 审中-公开

    公开(公告)号：US20180292449A1

    公开(公告)日：2018-10-11

    申请号：US15480388

    申请日：2017-04-06

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Kuei-Sheng Wu ,  Wen-Jung Liao ,  Wen-Shan Hsiao

    IPC: G01R31/26

    CPC classification number: G01R31/2601 ,  G01R31/2621

    Abstract: A testkey structure including the following components is provided. A fin structure is disposed on a substrate and stretches along a first direction. A first gate structure and a second gate structure are disposed on the fin structure and stretch along a second direction. A first common source region is disposed in the fin structure between the first gate structure and the second gate structure. A first drain region is disposed in the fin structure at a side of the first gate structure opposite to the first common source region. A second drain region disposed in the fin structure at a side of the second gate structure opposite to the first common source region. A testkey structure is symmetrical along a horizontal line crossing the first common source region. The present invention further provides a method of measuring device defect or connection defect by using the same.

    Interposer structure and manufacturing method thereof
    2.
    发明授权
    Interposer structure and manufacturing method thereof 有权
    内插器结构及其制造方法

    公开(公告)号：US09412686B2

    公开(公告)日：2016-08-09

    申请号：US14468329

    申请日：2014-08-26

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ming-Tse Lin ,  Kuei-Sheng Wu ,  Chien-Li Kuo

    IPC: H05K1/09 ,  H01L23/498 ,  H01L21/48 ,  H01L21/311

    CPC classification number: H01L23/49811 ,  H01L21/31111 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49866 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The present disclosure relates to an interposer structure and a manufacturing method thereof. The interposer structure includes a first dielectric layer, a conductive pad, and a bump. The conductive pad is disposed in the first dielectric layer, wherein a top surface of the conductive pad is exposed from a first surface of the first dielectric layer, the conductive pad further includes a plurality of connection feet, and the connection feet protrude from a bottom surface of the conductive pad to a second surface of the first dielectric layer. The bump is disposed on the second surface of the first dielectric layer, and the bump directly contacts to the connection feet. Through the aforementioned interposer structure, it is sufficient to achieve the purpose of improving the electrical performance of the semiconductor device and avoiding the signal being loss through the TSV.

    Abstract translation: 本发明涉及内插器结构及其制造方法。 插入器结构包括第一电介质层，导电焊盘和凸块。 所述导电焊盘设置在所述第一电介质层中，其中所述导电焊盘的顶表面从所述第一介电层的第一表面露出，所述导电焊盘还包括多个连接脚，并且所述连接脚从底部突出 导电焊盘的表面到第一介电层的第二表面。 凸块设置在第一电介质层的第二表面上，凸块直接接触连接脚。 通过上述插入器结构，达到提高半导体器件的电气性能并避免信号通过TSV损耗的目的就足够了。

    SEMICONDUCTOR STRUCTURE AND METHOD FOR TESTING THE SAME
    3.
    发明申请
    SEMICONDUCTOR STRUCTURE AND METHOD FOR TESTING THE SAME 审中-公开
    半导体结构及其测试方法

    公开(公告)号：US20140332952A1

    公开(公告)日：2014-11-13

    申请号：US13890397

    申请日：2013-05-09

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chien-Li Kuo ,  Yung-Chang Lin ,  Chun-Ting Yeh ,  Kuei-Sheng Wu

    IPC: H01L23/48 ,  H01L21/66

    CPC classification number: H01L23/481 ,  H01L22/14 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor structure comprising a substrate, a dielectric layer, a conductor post, a first conductive layer structure and a second conductive layer structure is provided. The substrate comprises an opening structure. The dielectric layer is disposed on a sidewall of the opening structure. The conductor structure is disposed in the opening structure and covers the dielectric layer. The first and second conductive layer structures are electrically connected to the conductor post. A voltage difference is existed between the first and second conductive layer structures, such that a current is passing through the first conductive layer structure, the opening structure and second conductive layer structure. A resistance values is related to the voltage difference and the current. A dimension of the opening structure is 10 times greater than a dimension of the first and second conductive layer structures.

    Abstract translation: 提供了包括基板，电介质层，导体柱，第一导电层结构和第二导电层结构的半导体结构。 基板包括开口结构。 电介质层设置在开口结构的侧壁上。 导体结构设置在开口结构中并覆盖电介质层。 第一和第二导电层结构电连接到导体柱。 在第一和第二导电层结构之间存在电压差，使得电流通过第一导电层结构，开口结构和第二导电层结构。 电阻值与电压差和电流有关。 开口结构的尺寸是第一和第二导电层结构的尺寸的10倍。

    METHOD FOR FABRICATION SEMICONDUCTOR DEVICE
    6.
    发明申请
    METHOD FOR FABRICATION SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20170330820A1

    公开(公告)日：2017-11-16

    申请号：US15663679

    申请日：2017-07-28

    Applicant: United Microelectronics Corp.

    Inventor： Kuei-Sheng Wu ,  Ming-Tse Lin

    IPC: H01L23/48 ,  H01L21/768 ,  H01L23/498 ,  H01L23/532

    CPC classification number: H01L23/481 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76898 ,  H01L23/49827 ,  H01L2224/02372 ,  H01L2225/06541

    Abstract: A method for is used for forming a semiconductor device. The method includes forming an ILD layer on a substrate and a buffer layer on the ILD layer, wherein at least one contact is formed in the ILD layer; forming an opening through the buffer layer, the ILD layer, and the substrate; forming a liner structure layer over the substrate, wherein an exposed surface of the opening is covered by the liner structure layer; depositing a conductive material over the substrate to fill the opening; performing a polishing process, to polish over the substrate and stop at the buffer layer, wherein the liner structure layer and the conductive material remaining in the opening form a conductive via; performing an etching back process, to remove the buffer layer and expose the ILD layer, wherein a top portion of the conductive via is also exposed and higher than the ILD layer.

    INTERPOSER STRUCTURE AND MANUFACTURING METHOD THEREOF
    7.
    发明申请
    INTERPOSER STRUCTURE AND MANUFACTURING METHOD THEREOF 有权
    接口结构及其制造方法

    公开(公告)号：US20160064314A1

    公开(公告)日：2016-03-03

    申请号：US14468329

    申请日：2014-08-26

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ming-Tse Lin ,  Kuei-Sheng Wu ,  Chien-Li Kuo

    IPC: H01L23/498 ,  H01L21/311 ,  H01L21/48

    CPC classification number: H01L23/49811 ,  H01L21/31111 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49866 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The present disclosure relates to an interposer structure and a manufacturing method thereof. The interposer structure includes a first dielectric layer, a conductive pad, and a bump. The conductive pad is disposed in the first dielectric layer, wherein a top surface of the conductive pad is exposed from a first surface of the first dielectric layer, the conductive pad further includes a plurality of connection feet, and the connection feet protrude from a bottom surface of the conductive pad to a second surface of the first dielectric layer. The bump is disposed on the second surface of the first dielectric layer, and the bump directly contacts to the connection feet. Through the aforementioned interposer structure, it is sufficient to achieve the purpose of improving the electrical performance of the semiconductor device and avoiding the signal being loss through the TSV.

    Abstract translation: 本发明涉及内插器结构及其制造方法。 插入器结构包括第一电介质层，导电焊盘和凸块。 所述导电焊盘设置在所述第一电介质层中，其中所述导电焊盘的顶表面从所述第一介电层的第一表面露出，所述导电焊盘还包括多个连接脚，并且所述连接脚从底部突出 导电焊盘的表面到第一介电层的第二表面。 凸块设置在第一电介质层的第二表面上，凸块直接接触连接脚。 通过上述插入器结构，达到提高半导体器件的电气性能并避免信号通过TSV损耗的目的就足够了。

    Testkey structure and method of measuring device defect or connection defect by using the same
    10.
    发明授权
    Testkey structure and method of measuring device defect or connection defect by using the same 有权

    公开(公告)号：US10145889B2

    公开(公告)日：2018-12-04

    申请号：US15480388

    申请日：2017-04-06

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Kuei-Sheng Wu ,  Wen-Jung Liao ,  Wen-Shan Hsiao

    IPC: G01R31/26

    Abstract: A testkey structure including the following components is provided. A fin structure is disposed on a substrate and stretches along a first direction. A first gate structure and a second gate structure are disposed on the fin structure and stretch along a second direction. A first common source region is disposed in the fin structure between the first gate structure and the second gate structure. A first drain region is disposed in the fin structure at a side of the first gate structure opposite to the first common source region. A second drain region disposed in the fin structure at a side of the second gate structure opposite to the first common source region. A testkey structure is symmetrical along a horizontal line crossing the first common source region. The present invention further provides a method of measuring device defect or connection defect by using the same.

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