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    Method of fabrication of an FeRAM capacitor and an FeRAM capacitor formed by the method
    2.
    发明授权
    Method of fabrication of an FeRAM capacitor and an FeRAM capacitor formed by the method 失效
    通过该方法形成FeRAM电容器和FeRAM电容器的制造方法

    公开(公告)号：US07001780B2

    公开(公告)日：2006-02-21

    申请号：US10635140

    申请日：2003-08-06

    申请人： Haoren Zhuang ,  Ulrich Egger ,  Jingyu Lian ,  Stefan Gernhardt ,  Hiroyuki Kanaya

    发明人： Haoren Zhuang ,  Ulrich Egger ,  Jingyu Lian ,  Stefan Gernhardt ,  Hiroyuki Kanaya

    IPC分类号： H01L21/00

    CPC分类号： H01L28/86 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/65 ,  H01L28/90

    摘要： A ferroelectric device includes a bottom electrode on which are formed ferrocapacitor elements and, over the ferroelectric elements, top electrodes. The bottom electrodes are connected to lower layers of the device via conductive plugs, and the plugs and bottom electrodes are spaced apart by barrier elements of Ir and/or IrO2. The barrier elements are narrower than the bottom electrode elements, and are formed by a separate etching process. This means that Ir fences are not formed during the etching of the bottom electrode. Also, little Ir and/or IrO2 diffuses through the bottom electrode to the ferroelectric elements, and therefore there is little risk of damage to the ferroelectric material.

    摘要翻译： 铁电体元件包括底电极，其上形成有铁电体元件，并且在铁电元件上形成顶电极。 底部电极通过导电插头连接到器件的下层，并且插头和底部电极被Ir和/或IrO 2的阻挡元件隔开。 阻挡元件比底部电极元件窄，并且通过单独的蚀刻工艺形成。 这意味着在底电极的蚀刻期间不形成Ir栅栏。 此外，很少的Ir和/或IrO 2 <2>通过底部电极扩散到铁电体元件，因此几乎不会损坏铁电体材料的风险。

    Method of fabrication of an FeRAM capacitor and an FeRAM capacitor formed by the method
    3.
    发明申请
    Method of fabrication of an FeRAM capacitor and an FeRAM capacitor formed by the method 失效
    通过该方法形成FeRAM电容器和FeRAM电容器的制造方法

    公开(公告)号：US20050029563A1

    公开(公告)日：2005-02-10

    申请号：US10635140

    申请日：2003-08-06

    申请人： Haoren Zhuang ,  Ulrich Egger ,  Jingyu Lian ,  Stefan Gernhardt ,  Hiroyuki Kanaya

    发明人： Haoren Zhuang ,  Ulrich Egger ,  Jingyu Lian ,  Stefan Gernhardt ,  Hiroyuki Kanaya

    IPC分类号： H01L21/02 ,  H01L21/8246 ,  H01L31/119

    CPC分类号： H01L28/86 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/65 ,  H01L28/90

    摘要： A ferroelectric device includes a bottom electrode on which are formed ferrocapacitor elements and, over the ferroelectric elements, top electrodes. The bottom electrodes are connected to lower layers of the device via conductive plugs, and the plugs and bottom electrodes are spaced apart by barrier elements of Ir and/or IrO2. The barrier elements are narrower than the bottom electrode elements, and are formed by a separate etching process. This means that Ir fences are not formed during the etching of the bottom electrode. Also, little Ir and/or IrO2 diffuses through the bottom electrode to the ferroelectric elements, and therefore there is little risk of damage to the ferroelectric material.

    摘要翻译： 铁电体元件包括底电极，其上形成有铁电体元件，并且在铁电元件上形成顶电极。 底部电极通过导电插头连接到器件的下层，并且插头和底部电极被Ir和/或IrO 2的屏障元件隔开。 阻挡元件比底部电极元件窄，并且通过单独的蚀刻工艺形成。 这意味着在底电极的蚀刻期间不形成Ir栅栏。 另外，少量Ir和/或IrO 2通过底部电极扩散到铁电体元件，因此几乎不会损坏铁电体材料。

    Semiconductor memory device having ferroelectric capacitors with hydrogen barriers
    6.
    发明授权
    Semiconductor memory device having ferroelectric capacitors with hydrogen barriers 失效
    具有具有氢屏障的铁电电容器的半导体存储器件

    公开(公告)号：US07400005B2

    公开(公告)日：2008-07-15

    申请号：US11142441

    申请日：2005-06-02

    申请人： Yoshinori Kumura ,  Iwao Kunishima ,  Hiroyuki Kanaya ,  Tohru Ozaki ,  Kazuhiro Tomioka

    发明人： Yoshinori Kumura ,  Iwao Kunishima ,  Hiroyuki Kanaya ,  Tohru Ozaki ,  Kazuhiro Tomioka

    IPC分类号： H01L29/92

    CPC分类号： H01L27/11502 ,  H01L27/11507 ,  H01L28/57 ,  H01L28/65

    摘要： A semiconductor memory device, which prevents the penetration of hydrogen or moisture to a ferroelectric capacitor from its surrounding area including a contact plug portion, comprises a ferroelectric capacitor formed above a semiconductor substrate, a first hydrogen barrier film formed on an upper surface of the ferroelectric capacitor to work as a mask in the formation of the ferroelectric capacitor, a second hydrogen barrier film formed on the upper surface and a side face of the ferroelectric capacitor including on the first hydrogen barrier film, and a contact plug disposed through the first and second hydrogen barrier films, and connected to an upper electrode of the ferroelectric capacitor, a side face thereof being surrounded with the hydrogen barrier films.

    摘要翻译： 一种半导体存储器件，其防止氢或水分从其包括接触插塞部分的周围区域渗入铁电电容器，包括形成在半导体衬底上的强电介质电容器，形成在铁电体的上表面上的第一氢阻挡膜 电容器在形成铁电电容器时用作掩模，在上表面上形成的第二氢阻挡膜和包括在第一氢阻挡膜上的强电介质电容器的侧面，以及通过第一和第二 氢阻挡膜，并连接到铁电电容器的上电极，其侧面被氢阻挡膜包围。

    Semiconductor memory device and its manufacturing method
    7.
    发明申请
    Semiconductor memory device and its manufacturing method 失效
    半导体存储器件及其制造方法

    公开(公告)号：US20060180894A1

    公开(公告)日：2006-08-17

    申请号：US11142441

    申请日：2005-06-02

    申请人： Yoshinori Kumura ,  Iwao Kunishima ,  Hiroyuki Kanaya ,  Tohru Ozaki ,  Kazuhiro Tomioka

    发明人： Yoshinori Kumura ,  Iwao Kunishima ,  Hiroyuki Kanaya ,  Tohru Ozaki ,  Kazuhiro Tomioka

    IPC分类号： H01L29/00

    CPC分类号： H01L27/11502 ,  H01L27/11507 ,  H01L28/57 ,  H01L28/65

    摘要： A semiconductor memory device, which prevents the penetration of hydrogen or moisture to a ferroelectric capacitor from its surrounding area including a contact plug portion, comprises a ferroelectric capacitor formed above a semiconductor substrate, a first hydrogen barrier film formed on an upper surface of the ferroelectric capacitor to work as a mask in the formation of the ferroelectric capacitor, a second hydrogen barrier film formed on the upper surface and a side face of the ferroelectric capacitor including on the first hydrogen barrier film, and a contact plug disposed through the first and second hydrogen barrier films, and connected to an upper electrode of the ferroelectric capacitor, a side face thereof being surrounded with the hydrogen barrier films.

    摘要翻译： 一种半导体存储器件，其防止氢或水分从其包括接触插塞部分的周围区域渗入铁电电容器，包括形成在半导体衬底上的强电介质电容器，形成在铁电体的上表面上的第一氢阻挡膜 电容器在形成铁电电容器时用作掩模，在上表面上形成的第二氢阻挡膜和包括在第一氢阻挡膜上的强电介质电容器的侧面，以及通过第一和第二 氢阻挡膜，并连接到铁电电容器的上电极，其侧面被氢阻挡膜包围。

    Semiconductor device and method of manufacturing the same
    8.
    发明申请
    Semiconductor device and method of manufacturing the same 审中-公开
    半导体装置及其制造方法

    公开(公告)号：US20050128663A1

    公开(公告)日：2005-06-16

    申请号：US10750814

    申请日：2004-01-05

    申请人： Soichi Yamazaki ,  Hiroyuki Kanaya ,  Kazuhiro Tomioka ,  Koji Yamakawa

    发明人： Soichi Yamazaki ,  Hiroyuki Kanaya ,  Kazuhiro Tomioka ,  Koji Yamakawa

    IPC分类号： H01L27/105 ,  H01L21/02 ,  H01L21/8246 ,  H01L27/115 ,  H02H9/00

    CPC分类号： H01L27/11507 ,  H01L27/11502 ,  H01L28/55 ,  H01L28/65 ,  H01L28/75

    摘要： There is disclosed a semiconductor device comprising a capacitor comprising a lower electrode provided above a substrate, a capacitor insulating film selectively provided on the lower electrode, and an upper electrode selectively provided above the lower electrode so that the capacitor insulating film can be interposed between the upper and lower electrodes, an electrode protection film formed of oxide conductors containing at least one of metal elements such as Sr, Ti, Ru, Ir and Pt, and provided on the upper electrode, an interlayer insulating film provided on the electrode protection film, an upper layer interconnect wire for the lower electrode provided on the interlayer insulating film, and electrically connected to the lower electrode, and an upper layer interconnect wire for the upper electrode provided on the interlayer insulating film, and electrically connected to the upper electrode.

    摘要翻译： 公开了一种半导体器件，其包括电容器，该电容器包括设置在基板上的下电极，选择性地设置在下电极上的电容器绝缘膜，以及选择性地设置在下电极上方的上电极，使得电容器绝缘膜可以介于 上下电极，由包含Sr，Ti，Ru，Ir和Pt等金属元素中的至少一种的氧化物导体形成的电极保护膜，设置在上部电极上，设置在电极保护膜上的层间绝缘膜， 用于下层电极的上层互连线设置在层间绝缘膜上并电连接到下电极，以及上层电介质线，用于上电极，设置在层间绝缘膜上，并电连接到上电极。

    Semiconductor memory device and manufacturing method thereof
    9.
    发明授权
    Semiconductor memory device and manufacturing method thereof 有权
    半导体存储器件及其制造方法

    公开(公告)号：US09171886B2

    公开(公告)日：2015-10-27

    申请号：US13032359

    申请日：2011-02-22

    申请人： Hiroyuki Kanaya ,  Yukinori Koyama ,  Susumu Shuto ,  Kuniaki Sugiura

    发明人： Hiroyuki Kanaya ,  Yukinori Koyama ,  Susumu Shuto ,  Kuniaki Sugiura

    IPC分类号： H01L29/82 ,  H01L27/22 ,  H01L21/768 ,  H01L43/12

    CPC分类号： H01L27/228 ,  H01L21/76897 ,  H01L43/12

    摘要： A semiconductor memory device according to embodiments includes a semiconductor substrate and plural switching transistors provided on the semiconductor substrate. In the semiconductor memory device, a contact plug is embedded between adjacent two of the switching transistors, and is insulated from gates of the adjacent two switching transistors. The contact plug is also electrically connected to a source or a drain of each of the adjacent two switching transistors, and an upper surface of the contact plug is at a position higher than an upper surface of the switching transistors. A memory element is provided on the upper surface of the contact plug and stores data. A wiring is provided on the memory element.

    摘要翻译： 根据实施例的半导体存储器件包括半导体衬底和设置在半导体衬底上的多个开关晶体管。 在半导体存储器件中，接触插头嵌入相邻的两个开关晶体管之间，并且与相邻的两个开关晶体管的栅极绝缘。 接触插塞也电连接到相邻的两个开关晶体管中的每一个的源极或漏极，并且接触插塞的上表面位于高于开关晶体管的上表面的位置。 存储元件设置在接触插头的上表面上并存储数据。 在存储元件上提供布线。

    Semiconductor storage device and method of manufacturing the same
    10.
    发明授权
    Semiconductor storage device and method of manufacturing the same 有权
    半导体存储装置及其制造方法

    公开(公告)号：US08786038B2

    公开(公告)日：2014-07-22

    申请号：US13230746

    申请日：2011-09-12

    申请人： Keiji Hosotani ,  Hiroyuki Kanaya

    发明人： Keiji Hosotani ,  Hiroyuki Kanaya

    IPC分类号： H01L29/82 ,  H01L21/00

    CPC分类号： H01L43/12 ,  H01L27/228 ,  H01L43/08

    摘要： A semiconductor storage device according to the present embodiment includes a selection element formed on a surface of a semiconductor substrate. A lower electrode is connected to the selection element. A magnetic tunnel junction element is provided on the lower electrode. An upper electrode is provided on the magnetic tunnel junction element. A growth layer is provided on the upper electrode and is composed of a conductive material and has a larger area than the upper electrode when viewed from above the surface of the semiconductor substrate. A wiring line is provided on the growth layer.

    摘要翻译： 根据本实施例的半导体存储装置包括形成在半导体衬底的表面上的选择元件。 下电极连接到选择元件。 在下电极上设置磁性隧道结元件。 上部电极设置在磁性隧道结元件上。 生长层设置在上电极上并由导电材料构成，并且当从半导体衬底的表面上方观察时具有比上电极大的面积。 在生长层上设置布线。