中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

28 records (took 0.015 seconds)

    METHOD FOR FORMING PROGRAMMABLE MEMORY
    1.
    发明申请
    METHOD FOR FORMING PROGRAMMABLE MEMORY 有权

    公开(公告)号：US20240397712A1

    公开(公告)日：2024-11-28

    申请号：US18792499

    申请日：2024-08-01

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Hsueh-Chun Hsiao ,  Yi-Ning Peng ,  Tzu-Yun Chang

    IPC: H10B41/30 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788

    Abstract: An array of programmable memory includes a first floating gate and a second floating gate disposed on a substrate along a first direction, two spacers disposed between and parallel to the first floating gate and the second floating gate, a first word line sandwiched by one of the spacers and the adjacent first floating gate, and a second word line sandwiched by the other one of the spacers and the adjacent second floating gate, and two first spacers disposed on the substrate, wherein one of the first spacer is disposed between the first word line and the first floating gate, and another spacer is disposed between the second word line and the second floating gate, wherein each spacer has substantially the same shape as each first spacer.

    Semiconductor structure and manufacturing method thereof
    3.
    发明授权
    Semiconductor structure and manufacturing method thereof 有权
    半导体结构及其制造方法

    公开(公告)号：US09406771B1

    公开(公告)日：2016-08-02

    申请号：US14854161

    申请日：2015-09-15

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Shih-Yin Hsiao ,  Hsueh-Chun Hsiao ,  Tzu-Yun Chang ,  Ching-Chung Yang

    IPC: H01L29/78 ,  H01L29/49 ,  H01L29/423 ,  H01L29/08 ,  H01L29/06 ,  H01L21/28 ,  H01L21/265

    CPC classification number: H01L29/4983 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/28035 ,  H01L21/28105 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/4916 ,  H01L29/7833

    Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate; a first and a second ion implantation regions of a first conductive type; a source and a drain diffusion regions formed in the first and the second ion implantation regions respectively; a channel diffusion region formed between the first and the second ion implantation regions; a gate layer disposed above the channel diffusion region and located between the source and the drain diffusion regions; and a third ion implantation region of a second conductive type formed in the gate layer, which extends in a first direction. The third ion implantation region is located above and covers two side portions of the channel diffusion region, the two side portions are adjacent to two edges, extending in a second direction perpendicular to the first direction, of the channel diffusion region.

    Abstract translation: 提供半导体结构及其制造方法。 半导体结构包括基板; 第一导电类型的第一和第二离子注入区域; 在第一和第二离子注入区域中形成的源极和漏极扩散区域; 形成在第一和第二离子注入区之间的沟道扩散区; 栅极层，其设置在所述沟道扩散区域的上方且位于所述源极和漏极扩散区域之间; 以及形成在所述栅极层中的沿第一方向延伸的第二导电类型的第三离子注入区。 第三离子注入区域位于沟道扩散区域的上方并覆盖两个侧面部分，两个侧面部分与沟道扩散区域的垂直于第一方向的第二方向延伸的两个边缘相邻。

    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    4.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20240395929A1

    公开(公告)日：2024-11-28

    申请号：US18337396

    申请日：2023-06-19

    Applicant: United Microelectronics Corp.

    Inventor： Chen-Yuan Lin ,  Yu-Cheng Lo ,  Tzu-Yun Chang

    IPC: H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66

    Abstract: A semiconductor device includes a gate structure, a first doped region, a second doped region, an isolation structure, an insulating layer and a field plate. The gate structure is located on a substrate. The first doped region and the second doped region are located at two sides of the gate structure. The isolation structure is located in the substrate between the first doped region and the second doped region, and is separated from the gate structure by a non-zero distance. The insulating layer extends continuously from a portion of a top surface of the gate structure to a portion of a top surface of the isolation structure. The field plate is located on the insulating layer and has the same potential as the gate structure.

    SEMICONDUCTOR MEMORY DEVICE AND FABRICATION METHOD THEREOF
    7.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND FABRICATION METHOD THEREOF 有权

    公开(公告)号：US20220293679A1

    公开(公告)日：2022-09-15

    申请号：US17224140

    申请日：2021-04-07

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wen-Hsin Hsu ,  Ko-Chi Chen ,  Tzu-Yun Chang ,  Chung-Tse Chen

    IPC: H01L27/24 ,  H01L45/00

    Abstract: A semiconductor memory device includes a substrate, a dielectric layer on the substrate, and a contact plug in the dielectric layer. An upper portion of the contact plug protrudes from a top surface of the dielectric layer. The upper portion of the contact plug acts as a first electrode. A buffer layer is disposed on the dielectric layer and beside the upper portion of the contact plug. A resistive-switching layer is disposed beside the buffer layer. A second electrode is disposed beside the resistive-switching layer.

    SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME
    8.
    发明申请
    SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME 审中-公开
    半导体结构及其形成方法

    公开(公告)号：US20150115461A1

    公开(公告)日：2015-04-30

    申请号：US14066845

    申请日：2013-10-30

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chih-Chou Yu ,  Hsueh-Chun Hsiao ,  Tzu-Yun Chang

    IPC: H01L23/538 ,  H01L21/768

    CPC classification number: H01L21/76898 ,  H01L21/8221 ,  H01L23/544 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L2223/54493 ,  H01L2224/9202 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2225/06596

    Abstract: A semiconductor structure and a method for forming the same are provided. The method includes following steps. A first wafer is provided, which includes a first region, a second region, and a first semiconductor device disposed in the first region. No semiconductor device is disposed in the second region. A second wafer is provided, which includes a third region, a fourth region and a second semiconductor device disposed in the third region. No semiconductor device is disposed in the fourth region. The first region of the first wafer is overlapped with the fourth region of the second wafer. The second region of the first wafer is overlapped with the third region of the second wafer. A first conductive through via is formed to pass through the fourth region of the second wafer and the first region of the first wafer to electrically connect to the first semiconductor device.

    Abstract translation: 提供半导体结构及其形成方法。 该方法包括以下步骤。 提供第一晶片，其包括第一区域，第二区域和设置在第一区域中的第一半导体器件。 在第二区域中不设置半导体器件。 提供第二晶片，其包括设置在第三区域中的第三区域，第四区域和第二半导体器件。 在第四区域中不设置半导体器件。 第一晶片的第一区域与第二晶片的第四区域重叠。 第一晶片的第二区域与第二晶片的第三区域重叠。 形成第一导电通孔以通过第二晶片的第四区域和第一晶片的第一区域以电连接到第一半导体器件。

Patent Agency Ranking