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39 条记录 (耗时 0.02 秒)

    Method for fabrication of in-laid metal interconnects
    1.
    发明授权
    Method for fabrication of in-laid metal interconnects 有权
    埋入式金属互连的制造方法

    公开(公告)号：US08367552B2

    公开(公告)日：2013-02-05

    申请号：US10526422

    申请日：2003-08-04

    申请人： Roel Daamen ,  Viet Nguyen Hoang ,  Romano Julma Oscar Maria Hoofman ,  Greja Johanna Adriana Maria Verheijden

    发明人： Roel Daamen ,  Viet Nguyen Hoang ,  Romano Julma Oscar Maria Hoofman ,  Greja Johanna Adriana Maria Verheijden

    IPC分类号： H01L21/302 ,  H01L21/461

    CPC分类号： H01L21/7684 ,  H01L21/7688

    摘要： The present invention relates to a method for fabrication of in-laid metal interconnects. The method comprises the steps of providing a substrate with a dielectric material on top thereof, depositing a protection layer on top of the dielectric material, depositing a sacrificial layer on top of the protection layer, the sacrificial layer having a mechanical strength that is lower than the mechanical strength of the protection layer, making an opening) through the sacrificial layer, through the protection layer and into the dielectric material, depositing a barrier layer in the opening and on the sacrificial layer, depositing metal material on the barrier layer, the metal material filling the opening, removing portions of the metal material existing beyond the opening by means of polishing, and removing the barrier layer and the sacrificial layer in one polishing step.

    摘要翻译： 本发明涉及一种内置金属互连的制造方法。 该方法包括以下步骤：在其顶部提供介电材料的基底，在电介质材料的顶部上沉积保护层，在保护层的顶部上沉积牺牲层，牺牲层的机械强度低于 保护层的机械强度，形成开口）穿过保护层并进入电介质材料，在开口和牺牲层上沉积阻挡层，在阻挡层上沉积金属材料，金属 填充开口的材料，通过抛光去除存在于开口之外的金属材料的部分，以及在一个抛光步骤中去除阻挡层和牺牲层。

    Method for fabrication of in-laid metal interconnects
    2.
    发明申请
    Method for fabrication of in-laid metal interconnects 有权
    埋入式金属互连的制造方法

    公开(公告)号：US20110097896A1

    公开(公告)日：2011-04-28

    申请号：US10526422

    申请日：2003-08-04

    申请人： Roel Daamen ,  Viet Nguyen Hoang ,  Romano Hoofman ,  Greja Verheijoen

    发明人： Roel Daamen ,  Viet Nguyen Hoang ,  Romano Hoofman ,  Greja Verheijoen

    IPC分类号： H01L21/768

    CPC分类号： H01L21/7684 ,  H01L21/7688

    摘要： The present invention relates to a method for fabrication of in-laid metal interconnects. The method comprises the steps of providing a substrate with a dielectric material (1) on top thereof, depositing a protection layer (2) on top of the dielectric material, depositing a sacrificial layer (7) on top of the protection layer, the sacrificial layer having a mechanical strength that is lower than the mechanical strength of the protection layer, making an opening (3) through the sacrificial layer, through the protection layer and into the dielectric material, depositing a barrier layer (4) in the opening and on the sacrificial layer, depositing metal material (5) on the barrier layer, the metal material filling the opening, removing portions of the metal material existing beyond the opening by means of polishing, and removing the barrier layer and the sacrificial layer in one polishing step.

    摘要翻译： 本发明涉及一种内置金属互连的制造方法。 该方法包括以下步骤：在其顶部提供介电材料（1）的基底，在电介质材料的顶部上沉积保护层（2），在保护层的顶部上沉积牺牲层（7） 具有低于保护层的机械强度的机械强度的层，通过保护层形成通过牺牲层的开口（3）并进入电介质材料，在开口中沉积阻挡层（4） 牺牲层，在阻挡层上沉积金属材料（5），填充开口的金属材料，通过抛光去除存在于开口之外的金属材料的部分，以及在一个抛光步骤中去除阻挡层和牺牲层 。

    Polishing apparatus and two-step method of polishing a metal layer of an integrated circuit
    3.
    发明授权
    Polishing apparatus and two-step method of polishing a metal layer of an integrated circuit 失效
    抛光装置和两步法抛光集成电路的金属层

    公开(公告)号：US07709387B2

    公开(公告)日：2010-05-04

    申请号：US10544411

    申请日：2004-01-23

    申请人： Viet Nguyen Hoang ,  Roel Daamen

    发明人： Viet Nguyen Hoang ,  Roel Daamen

    IPC分类号： H01L21/302

    CPC分类号： H01L21/3212 ,  H01L21/7684

    摘要： The method of manufacturing an integrated circuit (IC) according to the invention starts with providing a pre-fabricated integrated circuit (10) comprising an electrical device (2) and having a surface (11) coated with a dielectric material (12) and a metal (15). The dielectric material (12), which may be separated from the metal (15) by the barrier layer (14), has an opening (13), which is filled with the metal (15). Portions of the metal (15) outside the opening (13) are removed by polishing for a first period of time, after which an etching agent (25) is added to the polishing liquid (24) and polishing is continued for a second period of time for removing portions of the metal (15) remaining outside the opening (13). The polishing apparatus (40) is able to perform the method.

    摘要翻译： 根据本发明的制造集成电路（IC）的方法开始于提供一种包括电气装置（2）并具有涂覆有电介质材料（12）的表面（11）的预制集成电路（10）和 金属（15）。 可以通过阻挡层（14）与金属（15）分离的电介质材料（12）具有填充有金属（15）的开口（13）。 通过在第一时间内抛光除去开口（13）外部的金属部分（15），然后将蚀刻剂（25）加入到抛光液体（24）中，继续研磨第二周期 用于去除剩余在开口（13）外部的金属（15）的部分的时间。 抛光装置（40）能够执行该方法。

    Method of manufacturing a semiconductor device having damascene structures with air gaps
    4.
    发明授权
    Method of manufacturing a semiconductor device having damascene structures with air gaps 有权
    制造具有气隙的镶嵌结构的半导体器件的方法

    公开(公告)号：US07510959B2

    公开(公告)日：2009-03-31

    申请号：US11083344

    申请日：2005-03-16

    申请人： Roel Daamen ,  Viet Nguyen Hoang

    发明人： Roel Daamen ,  Viet Nguyen Hoang

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/7682

    摘要： A method of manufacturing a semiconductor device having damascene structures with air gaps is provided. In one embodiment, the method comprises the steps of depositing and patterning a disposable layer, depositing a first barrier layer on top of the patterned disposable layer, depositing a metal layer, planarizing the metal layer, depositing a second barrier layer, planarizing the second barrier layer until substantially no barrier layer material is present on top of the disposable layer, depositing a permeable layer, removing the disposable layer through the permeable layer to form air gaps.

    摘要翻译： 提供一种制造具有气隙的镶嵌结构的半导体器件的方法。 在一个实施例中，该方法包括以下步骤：沉积和图案化一次性层，在图案化的一次性层的顶部上沉积第一阻挡层，沉积金属层，平坦化金属层，沉积第二阻挡层，平坦化第二屏障 层，直到在一次性层的顶部上基本上没有阻挡层材料，沉积可渗透层，通过可渗透层去除一次性层以形成气隙。

    Integrated circuit manufacturing method
    5.
    发明授权
    Integrated circuit manufacturing method 有权
    集成电路制造方法

    公开(公告)号：US08772073B2

    公开(公告)日：2014-07-08

    申请号：US12988110

    申请日：2009-04-14

    申请人： Viet Nguyen Hoang ,  Radu Surdeanu ,  Benoit Bataillou

    发明人： Viet Nguyen Hoang ,  Radu Surdeanu ,  Benoit Bataillou

    IPC分类号： H01L21/00 ,  H01L27/146 ,  H01L21/3105

    CPC分类号： H01L27/14685 ,  H01L21/31053 ,  H01L21/31111 ,  H01L27/14621 ,  H01L27/14629

    摘要： A method of providing a dielectric material (18) having regions (18′, 18″) with a varying thickness in an IC manufacturing process is disclosed. The method comprises forming a plurality of patterns in respective regions (20′, 20″) of the dielectric material (18), each pattern increasing the susceptibility of the dielectric material (18) to a dielectric material removal step by a predefined amount and exposing the dielectric material (18) to the dielectric material removal step. In an embodiment, the IC comprises a plurality of pixilated elements (12) and a plurality of light interference elements (24), each comprising a first mirror element (16) and a second mirror element (22), a region of the dielectric material (18) separating the first mirror element (16) and the second element (22), and each being arranged over one of said pixilated elements (12), the method further comprising forming the respective first mirror elements (16) in a dielectric layer (14) over a substrate (10) comprising the plurality of pixilated elements; depositing the dielectric material over the dielectric layer; and forming the respective second mirror elements such that each second mirror element is separated from a respective first mirror element by a region of the exposed dielectric material. Hence, an IC having a layer of a dielectric material (18) comprising regions of different thicknesses can be obtained requiring only a few process steps.

    摘要翻译： 公开了一种在IC制造过程中提供具有变化厚度的区域（18'，18“）的介电材料（18）的方法。 该方法包括在介电材料（18）的相应区域（20'，20“）中形成多个图案，每个图案将电介质材料（18）的敏感性增加到电介质材料去除步骤预定量并暴露 介电材料（18）到介电材料去除步骤。 在一个实施例中，IC包括多个像素化元件（12）和多个光干涉元件（24），每个元件包括第一镜元件（16）和第二镜元件（22），介电材料的区域 （18）分离第一镜元件（16）和第二元件（22），并且每个被布置在一个所述像素化元件（12）上，所述方法还包括在电介质层中形成相应的第一镜元件（16） （14）包括多个像素化元件的衬底（10）上; 在电介质层上沉积电介质材料; 以及形成各个第二反射镜元件，使得每个第二反射镜元件通过暴露的电介质材料的区域与相应的第一反射镜元件分离。 因此，可以获得具有包括不同厚度的区域的电介质材料层（18）的IC，只需要几个工艺步骤。

    Method of controlling an LED, and an LED controller
    6.
    发明授权
    Method of controlling an LED, and an LED controller 有权
    控制LED的方法和LED控制器

    公开(公告)号：US08723443B2

    公开(公告)日：2014-05-13

    申请号：US13257266

    申请日：2010-02-25

    申请人： Peter Hubertus Franciscus Deurenberg ,  Gert-Jan Koolen ,  Gian Hoogzaad ,  Radu Surdeanu ,  Pascal Bancken ,  Benoit Bataillou ,  Viet Nguyen Hoang

    发明人： Peter Hubertus Franciscus Deurenberg ,  Gert-Jan Koolen ,  Gian Hoogzaad ,  Radu Surdeanu ,  Pascal Bancken ,  Benoit Bataillou ,  Viet Nguyen Hoang

    IPC分类号： H05B33/00

    CPC分类号： H05B33/086 ,  H05B33/0815 ,  H05B33/0848

    摘要： A method is disclosed of controlling a LED, comprising driving the LED with a DC current for a first time, interrupting the DC current for a second time such that the first time and the second time sum to a period, determining at least one characteristic of the LED while the DC current is interrupted, and controlling the DC current during a subsequent period in dependence on the at least one characteristic. The invention thus benefits from the simplicity of DC operation. By operating at the LED in a DC mode, rather than say in a PWM mode, the requirement to be able to adjust the duty cycle is avoided. By including interruptions to the DC current, it is possible to utilize the LED itself to act as a sensor in order to determine a characteristic of the LED. The need for additional sensors is thereby avoided.

    摘要翻译： 公开了一种控制LED的方法，包括第一次用DC电流驱动LED，第二次中断DC电流，使得第一时间和第二时间总和到一个周期，确定至少一个特性 所述LED在DC电流中断期间，并且根据所述至少一个特性在随后的时段期间控制所述DC电流。 因此，本发明由于DC操作的简单性而受益。 通过在DC模式下操作LED，而不是在PWM模式下说明，可以避免能够调整占空比的要求。 通过包含直流电流的中断，可以利用LED本身作为传感器，以便确定LED的特性。 从而避免了对附加传感器的需要。

    Planarising damascene structures
    7.
    发明授权
    Planarising damascene structures 有权
    平面镶嵌结构

    公开(公告)号：US08012872B2

    公开(公告)日：2011-09-06

    申请号：US11718876

    申请日：2005-11-02

    申请人： Viet Nguyen Hoang ,  Greja J. A. M. Verheijden

    发明人： Viet Nguyen Hoang ,  Greja J. A. M. Verheijden

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76843 ,  H01L21/3212 ,  H01L21/7684 ,  H01L21/76865

    摘要： Manufacturing a damascene structure involves: forming a sacrificial layer (20) on a substrate (10) to protect an area around a recess (30) for the damascene structure, forming a barrier layer (40) in the recess, and in electrical contact with the sacrificial layer, forming the damascene structure (50) in the recess, and planarizing. During the planarizing the sacrificial layer reacts electrochemically with the barrier layer or with the damascene structure. This can alter a relative rate of removal of the damascene structure and the sacrificial layer so as to reduce dishing or protrusion of the damascene structure, and reduce copper residues, and reduce barrier corrosion. The barrier layer can be formed by ALCVD. The barrier material being one or more of WCN and TaN. The sacrificial layer can be TaN, TiN or W.

    摘要翻译： 制造镶嵌结构包括：在基底（10）上形成牺牲层（20）以保护用于镶嵌结构的凹部（30）周围的区域，在凹槽中形成阻挡层（40），并与 牺牲层，在凹部中形成镶嵌结构（50）并且平坦化。 在平坦化期间，牺牲层与阻挡层或镶嵌结构电化学反应。 这可以改变镶嵌结构和牺牲层的相对去除速率，以减少镶嵌结构的凹陷或凸起，并且减少铜残留物，并减少屏障腐蚀。 阻挡层可以通过ALCVD形成。 阻挡材料是WCN和TaN中的一种或多种。 牺牲层可以是TaN，TiN或W.