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公开(公告)号：US11269365B2
公开(公告)日：2022-03-08
申请号：US16952873
申请日：2020-11-19
Applicant: Winbond Electronics Corp.
Inventor： Hiroki Murakami
Abstract: The invention provides a voltage-generating circuit with a simple configuration capable of saving space and generating reliable voltage. The voltage-generating circuit of the invention includes a reference voltage-generating unit, a PTAT voltage-generating unit, a comparison unit, and a selection unit. The reference voltage-generating unit generates a reference voltage essentially without dependency on temperature. The PTAT voltage-generating unit generates a temperature-dependent voltage with a positive or negative dependency on temperature. The temperature-dependent voltage is equal to the reference voltage at a target temperature. The comparison unit compares the reference voltage with the temperature-dependent voltage. The selection unit selects and outputs either the reference voltage or the temperature-dependent voltage.
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公开(公告)号：US09153335B2
公开(公告)日：2015-10-06
申请号：US14301344
申请日：2014-06-11
Applicant: Winbond Electronics Corp.
Inventor： Hiroki Murakami , Kenichi Arakawa
CPC classification number: G11C16/24 , G11C16/0483 , G11C16/28 , G11C16/30
Abstract: The invention provides a clamp voltage generating circuit capable of generating a correct clamp voltage. The clamp voltage generating circuit includes an emulate transistor, having a drain coupled to a power source VDD, a source coupled to a node, and a gate coupled to the clamp voltage; a current setting circuit, connected between the node and ground, for setting a current flowing from the node to the ground; a regulator, inputting a feedback voltage from the node and a reference voltage, and outputting a voltage VCLMP. The current setting circuit duplicates a current of a bit line, so that the emulate transistor is similar to a charge transfer transistor.
Abstract translation: 本发明提供一种能产生正确钳位电压的钳位电压发生电路。 钳位电压产生电路包括仿真晶体管，其具有耦合到电源VDD的漏极，耦合到节点的源极和耦合到钳位电压的栅极; 连接在节点和地之间的电流设定电路，用于设定从节点流向地面的电流; 调节器，输入来自节点的反馈电压和参考电压，并输出电压VCLMP。 电流设置电路复制位线的电流，使得仿真晶体管类似于电荷转移晶体管。
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公开(公告)号：US10817189B2
公开(公告)日：2020-10-27
申请号：US15840594
申请日：2017-12-13
Applicant: Winbond Electronics Corp.
Inventor： Hiroki Murakami , Makoto Senoo
IPC: G06F3/00 , G11C16/00 , G06F3/06 , G11C29/02 , G11C16/26 , G11C16/16 , G11C29/46 , G11C29/12 , G11C29/56 , G11C29/04
Abstract: A semiconductor memory device is provided. The semiconductor memory device includes a memory cell array, a read only memory (ROM), a central processing unit, and a random access memory (RAM). The memory cell array stores data related to operating conditions of the semiconductor memory device. The ROM stores data used to control an operation of the semiconductor memory device. The central processing unit controls the operation of the semiconductor memory device according to the data read from the ROM. The central processing unit reads the data related to the operating conditions from the memory cell array in response to a requested operation and then temporarily stores the read data related to the operating conditions in the RAM. The central processing unit further reads the data related to the data related to the operating conditions from the RAM for controlling the operation of the semiconductor memory device.
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公开(公告)号：US10510421B2
公开(公告)日：2019-12-17
申请号：US16192775
申请日：2018-11-15
Applicant: Winbond Electronics Corp.
Inventor： Kazuki Yamauchi , Makoto Senoo , Hiroki Murakami
Abstract: A semiconductor storage device with a smaller chip size than prior art and a readout method are provided. The semiconductor storage device includes a memory cell array; a page buffer/sense circuit having a sensing node for sensing readout data from a selected page of the memory cell array and a latch circuit for holding data sensed by the sensing node; and a controller controls operations on the memory cell array. The sensing node includes an NMOS capacitor.
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公开(公告)号：US10297295B2
公开(公告)日：2019-05-21
申请号：US15692381
申请日：2017-08-31
Applicant: Winbond Electronics Corp.
Inventor： Hiroki Murakami , Makoto Senoo
IPC: G11C7/10 , G11C7/22 , G11C8/18 , G11C11/4093 , G11C16/04 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/32
Abstract: A semiconductor memory device which is capable of high-speed operation in synchronization with external control signals is provided. The semiconductor memory device has a data input portion, a memory array, a data output portion, and a control portion. The data input portion receives command and address input data in response to the external control signals. The memory array has a plurality of memory elements. The data output portion outputs data read from the memory array in response to the external control signals. The control portion has the function of delay-compensation. During the time interval for receiving the input data, the function of delay-compensation estimates the delay time of the internal circuits, stores the estimated delay-time in a memory unit, and adjusts the output timing of the data output portion.
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Patent Agency Ranking
6.发明授权公开(公告)号：US10269409B2
公开(公告)日：2019-04-23
申请号：US15613285
申请日：2017-06-05
Applicant: Winbond Electronics Corp.
Inventor： Hiroki Murakami
IPC: G11C11/408 , G11C8/08 , G11C8/14 , G11C11/4074 , G11C11/4099 , G11C11/56 , G11C16/04 , G11C16/08 , G11C16/30
Abstract: A non-volatile semiconductor memory device and a driving method for word lines thereof are provided. A flash memory of the invention includes a memory cell array including blocks and a block selection element selecting the block of the memory cell array based on row address information and including a block selection transistor, a level shifter, a boost circuit and a voltage supplying element. The block selection transistor is connected to each word line of the block. The level shifter supplies a voltage to a node connected to a gate of the block selection transistor. The boost circuit boosts a potential of the node. The voltage supplying element supplies an operation voltage to one of the terminals of the block selection transistor. The node, after performing first boosting by the operating voltage supplied by the supplying element, performs second boosting by the second circuit.
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公开(公告)号：US20230087732A1
公开(公告)日：2023-03-23
申请号：US17846017
申请日：2022-06-22
Applicant: Winbond Electronics Corp.
Inventor： Hiroki Murakami
IPC: G05F1/565
Abstract: Disclosed is a voltage generating circuit including a reference voltage generating part, a leakage current monitoring part, a control part, and an internal voltage generating part. The reference voltage generating part generates a reference voltage. The leakage current monitoring part generates a monitoring leakage current corresponding to a leakage current of an internal circuit of a semiconductor device. The control part controls the reference voltage according to the monitoring leakage current. The internal voltage generating part receives the reference voltage being controlled by the control part, and supplies an internal voltage to the internal circuit according to the controlled reference voltage. A semiconductor device including the same is also disclosed.
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公开(公告)号：US10990119B2
公开(公告)日：2021-04-27
申请号：US16784663
申请日：2020-02-07
Applicant: Winbond Electronics Corp.
Inventor： Hiroki Murakami
Abstract: A reference voltage generation circuit of the invention includes: PMOS transistors P1 and P2 configured to provide current sources with same current to a first current path and a second current path; a bipolar transistor Q1 connected to the PMOS transistors P1 on the first current path; a bipolar transistor Q2 connected to the PMOS transistors P2 on the second current path; a differential amplifier AMP controlling the gates of the PMOS transistors P1 and P2, such that a voltage of a node VN and a voltage of a node VP are equal; an output node BGR outputting a reference voltage Vref; and a reference voltage guarantee portion 130 outputting a detecting signal BGRDET when a differences between the voltage of the node VN and the voltage of the node VP is maintained below a determined value.
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公开(公告)号：US10938301B2
公开(公告)日：2021-03-02
申请号：US16743324
申请日：2020-01-15
Applicant: Winbond Electronics Corp.
Inventor： Hiroki Murakami
Abstract: A charge pump circuit that suppresses low boost efficiency is provided. The charge pump circuit 100 of the invention includes a main pump circuit CPn_M and a gate controlling pump circuit CPn_G controlling the main pump circuit CPn_M. The main pump circuit has the same basic configuration as the controlling pump circuit, which are both KER-type pump circuits. The controlling pump circuit controls the operation of a transistor of the main pump circuit after the main pump circuit is boosted, so that reverse current will not flow from the main pump circuit to the forward section of the pump circuit.
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公开(公告)号：US10665304B2
公开(公告)日：2020-05-26
申请号：US16209115
申请日：2018-12-04
Applicant: Winbond Electronics Corp.
Inventor： Makoto Senoo , Hiroki Murakami , Kazuki Yamauchi
IPC: G11C7/10 , G11C16/32 , G11C16/04 , G11C16/30 , G11C16/08 , G11C16/10 , G11C7/22 , G11C16/26 , G11C7/20
Abstract: A semiconductor memory device which is able to perform a power sequence with high reliability is provided. When a power from an external device is supplied, the controller of the flash memory of the invention is configured to read codes stored in a read-only memory in synchronization with a clock signal to perform a power-on sequence. In addition, the controller is further configured to deactivate the clock signal so as to pause the power-on sequence when it has been detected during the power-on sequence that the voltage of the power is not greater than a threshold, and to activate the clock signal to resume the power-on sequence when it is detected that the voltage of the supplied power exceeds the threshold again.
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