公开(公告)号：US11709521B1

公开(公告)日：2023-07-25

申请号：US16913716

申请日：2020-06-26

Applicant: Xilinx, Inc.

Inventor： Frederic Revenu ,  Frank Mueller ,  Thomas O. Satter ,  Mehrdad Eslami Dehkordi ,  Garik Mkrtchyan ,  Satish B. Sivaswamy ,  Nicholas A. Mezei ,  Chun Zhang

IPC: G06F1/06

CPC classification number: G06F1/06

Abstract: Synthetizing a hardware description language code into a netlist comprising loads and a multi-clock buffer (MBUF). The MBUF receives a global clocking signal and generates a first and a second related clocking signals. The loads are grouped into a first and a second groups receiving the first and the second clocking signals respectively. A first/second clock modifying leaf are placed between a common node and the first/group groups respectively, wherein the common node is positioned closer in proximity to the first/second groups in comparison to a clock source generating the global clocking signal. The first/second clock modifying leaves receive a least divided clocking signal from the MBUF and generate the first/second clocking signals respectively. The least divided clocking signal is routed from the MBUF to the first/second clock modifying leaves. The first/second clocking signals are routed from the first/second clock modifying leaves to the first/second group respectively.

公开(公告)号：US10242150B1

公开(公告)日：2019-03-26

申请号：US15175897

申请日：2016-06-07

Applicant: Xilinx, Inc.

Inventor： Sabyasachi Das ,  Xiaojian Yang ,  Niyati Shah ,  Govinda Keshavdas ,  Frederic Revenu

IPC: G06F17/50

Abstract: Circuit design implementation can include selecting a first and second load each having a control pin of a same type driven by a different driver, determining whether the driver of the first load matches the driver of the second load, and modifying the circuit design to drive the control pins of the first load and the second load using the driver of the first load. Circuit design implementation can include selecting a net having a driver and a plurality of loads exceeding a threshold, determining a selected module of the circuit design having a number of the plurality of loads of the net that meet a cloning criteria, and, in response, modifying the circuit design by creating a clone of the driver within the selected module and driving each load of the net within the selected module with the clone of the driver.

公开(公告)号：US09836568B1

公开(公告)日：2017-12-05

申请号：US15069524

申请日：2016-03-14

Applicant: Xilinx, Inc.

Inventor： Ilya K. Ganusov ,  Aaron Ng ,  Ronald E. Plyler ,  Sabyasachi Das ,  Frederic Revenu

IPC: G06F9/455 ,  G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5081

Abstract: Improving timing of a circuit design may include determining, using a processor, critical feed-forward paths of the circuit design, determining, using the processor, a sequential loop having a largest loop delay within the circuit design, and iteratively cutting, using the processor, the critical feed-forward paths and feed-forward paths parallel to the cut critical feed-forward paths until a stopping condition is met. The stopping condition may be determined according to the largest loop delay. The circuit design may be modified by inserting a register at each cut feed-forward path.

公开(公告)号：US11714950B2

公开(公告)日：2023-08-01

申请号：US17382621

申请日：2021-07-22

Applicant: Xilinx, Inc.

Inventor： Veeresh Pratap Singh ,  Meghraj Kalase ,  John Blaine ,  Srinivasan Dasasathyan ,  Padmini Gopalakrishnan ,  Frederic Revenu ,  Veena Johar ,  Pawan Kumar Singh ,  Mohit Sharma ,  Kameshwar Chandrasekar

IPC: G06F30/392 ,  G06F30/398 ,  G06F30/327 ,  G06F30/31

CPC classification number: G06F30/398 ,  G06F30/31 ,  G06F30/327 ,  G06F30/392

Abstract: Processing a circuit design includes stabilizing the circuit design by a design tool that performs one or more iterations of implementation, optimization assessment, optimization, and stability assessment until a threshold stability level is achieved. The design tool determines, in response to satisfaction of the threshold stability level, different strategies based on features of the circuit design and likelihood that use of the strategies would improve timing. Each strategy includes parameter settings for the design tool. The design tool executes multiple implementation flows using different sets of strategies to generate alternative implementations. One implementation of the alternative implementations nearest to satisfying a timing requirement is selected. The selected implementation is iteratively optimized to satisfy the timing requirement, while restricting changes to placement of cells and nets on a critical path of the one implementation to less than a threshold portion of cells and nets on the critical path.

公开(公告)号：US11681846B1

公开(公告)日：2023-06-20

申请号：US17147163

申请日：2021-01-12

Applicant: XILINX, INC.

Inventor： Xiaojian Yang ,  Frederic Revenu ,  Dinesh D. Gaitonde ,  Amit Gupta

IPC: G06F30/343 ,  G06F30/347

CPC classification number: G06F30/343 ,  G06F30/347

Abstract: A method of FPGA compilation for an emulation system includes receiving a netlist for an FPGA, partitioning the netlist into a set of sub-FPGA netlists, and mapping each of the sub-FPGA netlists in the set to a corresponding dynamic sub-FPGA region of the FPGA. The method further includes implementing the sub-FPGA netlists of the set in parallel to obtain a corresponding set of sub-FPGA bitstreams.

公开(公告)号：US20230034736A1

公开(公告)日：2023-02-02

申请号：US17382621

申请日：2021-07-22

Applicant: Xilinx, Inc.

Inventor： Veeresh Pratap Singh ,  Meghraj Kalase ,  John Blaine ,  Srinivasan Dasasathyan ,  Padmini Gopalakrishnan ,  Frederic Revenu ,  Veena Johar ,  Pawan Kumar Singh ,  Mohit Sharma ,  Kameshwar Chandrasekar

IPC: G06F30/398 ,  G06F30/31 ,  G06F30/327 ,  G06F30/392

Abstract: Processing a circuit design includes stabilizing the circuit design by a design tool that performs one or more iterations of implementation, optimization assessment, optimization, and stability assessment until a threshold stability level is achieved. The design tool determines, in response to satisfaction of the threshold stability level, different strategies based on features of the circuit design and likelihood that use of the strategies would improve timing. Each strategy includes parameter settings for the design tool. The design tool executes multiple implementation flows using different sets of strategies to generate alternative implementations. One implementation of the alternative implementations nearest to satisfying a timing requirement is selected. The selected implementation is iteratively optimized to satisfy the timing requirement, while restricting changes to placement of cells and nets on a critical path of the one implementation to less than a threshold portion of cells and nets on the critical path.