公开(公告)号：US10824786B1

公开(公告)日：2020-11-03

申请号：US15285786

申请日：2016-10-05

Applicant: Xilinx, Inc.

Inventor： Jun Liu ,  Hao Yu ,  Raymond Kong ,  David P. Schultz

IPC: G06F17/50 ,  G06F30/394 ,  G06F30/34 ,  G06F30/327 ,  G06F30/392 ,  G06F30/347

Abstract: Method, apparatus and computer-readable medium for providing a partial reconfiguration of a reconfigurable module are described. In one example, a method reads a netlist for a design of a circuit comprising a reconfigurable module and sets the reconfigurable module to a first region. The method then generates a second region that encompasses the first region and places the design with the first region. The method routes the design with the second region and generates a partial bitstream for the reconfigurable module.

公开(公告)号：US20200092230A1

公开(公告)日：2020-03-19

申请号：US16133357

申请日：2018-09-17

Applicant: Xilinx, Inc.

Inventor： David P. Schultz ,  Ian A. Swarbrick ,  Jun Liu ,  Raymond Kong ,  Herve Alexanian

IPC: H04L12/931 ,  G06F15/78 ,  H04L12/933

Abstract: Examples described herein provide for an electronic circuit, such as a System-on-Chip (SoC), having a Network-on-Chip (NoC). The NoC is configurable and has capabilities to be partially reconfigured. In an example, a NoC on an integrated circuit is configured. Subsystems on the integrated circuit communicate via the NoC. The NoC is partially reconfigured. A first subset of the NoC is reconfigured during the partial reconfiguration, and a second subset of the NoC is capable of continuing to pass communications uninterruptedly during the partial reconfiguration. After the partial reconfiguration, two or more of the subsystems communicate via the first subset of the NoC.

公开(公告)号：US10305511B1

公开(公告)日：2019-05-28

申请号：US15990151

申请日：2018-05-25

Applicant: Xilinx, Inc.

Inventor： David P. Schultz ,  Weiguang Lu ,  Priyanka Agrawal ,  Jun Liu ,  Sourabh Goyal ,  David Robinson

IPC: H03M7/46 ,  G06F17/50

Abstract: Decompressing a data set includes inputting data units to a decompression circuit and comparing each input data unit to a run value and to a substitute value. In response to the data unit being not equal to the run value or the substitute value, the decompression circuit outputs the value of the input data unit; in response to the input data unit having the run value and a succeeding data unit having a value N not equal to zero or one, the decompression circuit outputs multiple data units having the run value based on the value N; in response to input data unit having the substitute value, the decompression circuit outputs one data unit having the run value; and in response to one input data unit having the run value and a succeeding data unit equal to zero or one, the decompression circuit outputs one data unit of the substitute value.

公开(公告)号：US10031760B1

公开(公告)日：2018-07-24

申请号：US15160993

申请日：2016-05-20

Applicant: Xilinx, Inc.

Inventor： Sonal Santan ,  Raymond Kong ,  Yenpang Lin ,  Jun Liu ,  Ashish Gupta ,  Spenser Gilliland ,  Brian S. Martin

IPC: G06F15/177 ,  G06F9/4401

Abstract: Managing an accelerator may include responsive to determining a first container including a first configuration file and a second configuration file, caching, using a host processor, the second configuration file within a local memory of the host processor. The first configuration file may be provided, using the host processor, to a device of the accelerator. Responsive to a configuration event, the host processor may provide the cached second configuration file from the local memory to the device of the accelerator.

公开(公告)号：US09281807B1

公开(公告)日：2016-03-08

申请号：US14299196

申请日：2014-06-09

Applicant: Xilinx, Inc.

Inventor： Pierre Maillard ,  Praful Jain ,  Michael J. Hart ,  Sundeep Ram Gopal Agarwal ,  Austin H. Lesea ,  Jun Liu

IPC: H03K3/023 ,  H03K3/037

CPC classification number: H03K3/35625 ,  H03K3/356156

Abstract: A master-slave flip-flop implemented in an integrated circuit comprises a master latch coupled to receive data at an input; and a slave latch coupled to an output of the master latch, wherein the slave latch comprises an SEU-enhanced latch, and the master latch is not enhanced for SEU protection. A method of implementing a master-slave flip-flop in an integrated circuit is also described.

Abstract translation: 在集成电路中实现的主从触发器包括耦合以在输入端接收数据的主锁存器; 以及耦合到主锁存器的输出的从锁存器，其中从锁存器包括SEU增强锁存器，并且主锁存器不增强用于SEU保护。 还描述了在集成电路中实现主从触发器的方法。

公开(公告)号：US11652481B2

公开(公告)日：2023-05-16

申请号：US17405073

申请日：2021-08-18

Applicant: XILINX, INC.

Inventor： Pierre Maillard ,  Betty Lau ,  Yanran Chen ,  Jun Liu ,  Martin L. Voogel

IPC: H03K19/003 ,  G06F30/392 ,  H03K19/20 ,  H03K3/0233 ,  G06F30/30

CPC classification number: H03K19/003 ,  G06F30/30 ,  G06F30/392 ,  H03K3/0233 ,  H03K19/20

Abstract: One example of the present disclosure is an integrated circuit (IC). The IC includes an inverter with an input and an output, a clock transmission gate coupled to the output of the inverter; and a plurality of storage cells. The clock transmission gate is coupled to each of the plurality of storage cells, wherein each of the plurality of storage cells comprises a plurality of nodes arranged based on a minimum spacing.

公开(公告)号：US20200028511A1

公开(公告)日：2020-01-23

申请号：US16041602

申请日：2018-07-20

Applicant: Xilinx, Inc.

Inventor： Hao Yu ,  Raymond Kong ,  Brian S. Martin ,  Jun Liu

IPC: H03K19/177 ,  G06F17/50

Abstract: Hierarchical partial reconfiguration for integrated circuits includes converting, using computer hardware, a first partial reconfiguration module of a circuit design into a first partial reconfiguration container, wherein the circuit design is placed and routed, loading, using the computer hardware, a first netlist into the first partial reconfiguration container, wherein the first netlist includes a first plurality of partial reconfiguration modules that are initially empty, and including, using the computer hardware, a further netlist within each of the first plurality of partial reconfiguration modules. Using the computer hardware, the first partial reconfiguration container is implemented with the first plurality of partial reconfiguration modules being implemented within the first partial reconfiguration container.

公开(公告)号：US10296699B1

公开(公告)日：2019-05-21

申请号：US15468021

申请日：2017-03-23

Applicant: Xilinx, Inc.

Inventor： Hao Yu ,  Raymond Kong ,  Jun Liu

IPC: G06F17/50

Abstract: Implementing a circuit design for partial reconfiguration can include routing, using a processor, a net of the circuit design that connects an endpoint within a reconfigurable module with an endpoint within static circuitry external to the reconfigurable module and forming, using the processor, a set of candidate nodes including nodes used to route the net. A node from the set of candidate nodes is determined as the partition pin for partial reconfiguration.

公开(公告)号：US12026444B2

公开(公告)日：2024-07-02

申请号：US17522834

申请日：2021-11-09

Applicant: Xilinx, Inc.

Inventor： Hao Yu ,  Jun Liu

IPC: G06F30/343 ,  G06F30/327 ,  G06F30/347

CPC classification number: G06F30/343 ,  G06F30/327 ,  G06F30/347

Abstract: Dynamic port handling for circuit designs can include inserting, within a static isolated module of a circuit design, static drivers configured to drive isolated modules of reconfigurable module (RM) instances for inclusion in an RM of the circuit design. For each RM instance of a plurality of RM instances to be inserted into the RM, one or more additional ports can be inserted in the RM based on a number of isolated modules included in a current RM instance. Further, net(s) corresponding to the additional port(s) can be created. The circuit design, including the current RM instance, the additional port(s), and the net(s), can be placed and routed. Prior to the inserting and the performing place and route for a next RM instance to be inserted into the RM, the current RM instance can be removed from the RM along with the additional port(s) and the net(s).

公开(公告)号：US11177795B1

公开(公告)日：2021-11-16

申请号：US16855962

申请日：2020-04-22

Applicant: XILINX, INC.

Inventor： Jun Liu ,  Bruce Young

IPC: H03K3/037

Abstract: A master latch includes a latch input node and a latch output node, a first inverter with an input and an output, the input coupled to the latch input node and the output coupled to the latch output node, and a second inverter with an input and an output, the input coupled to the latch output node and the output coupled to the latch input node. The master latch further includes a first pull-up device connected between a source voltage and the latch input node, the first pull-up device configured to pull the latch input node up towards the source voltage when the latch output node is low, and a first pull-down device connected between the latch input node and a ground voltage, the first pull-down device configured to pull the latch input node towards the ground voltage when the latch output node is high.