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公开(公告)号:US09947716B2
公开(公告)日:2018-04-17
申请号:US15358852
申请日:2016-11-22
Applicant: XINTEC INC.
Inventor: Yen-Shih Ho , Hsiao-Lan Yeh , Chia-Sheng Lin , Yi-Ming Chang , Po-Han Lee , Hui-Hsien Wu , Jyun-Liang Wu , Shu-Ming Chang , Yu-Lung Huang , Chien-Min Lin
IPC: H01L27/146 , H01L21/48 , H01L21/67 , H01L23/18
CPC classification number: H01L27/14698 , H01L21/4803 , H01L21/67017 , H01L21/67132 , H01L23/18 , H01L27/14618 , H01L27/14634 , H01L27/14636 , H01L27/14687
Abstract: A chip package includes a chip, an adhesive layer, and a dam element. The chip has a sensing area, a first surface, and a second surface that is opposite to the first surface. The sensing area is located on the first surface. The adhesive layer covers the first surface of the chip. The dam element is located on the adhesive layer and surrounds the sensing area. The thickness of the dam element is in a range from 20 μm to 750 μm, and the wall surface of the dam element surrounding the sensing area is a rough surface.
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公开(公告)号:US09875912B2
公开(公告)日:2018-01-23
申请号:US15358098
申请日:2016-11-21
Applicant: XINTEC INC.
Inventor: Yen-Shih Ho , Hsiao-Lan Yeh , Chia-Sheng Lin , Yi-Ming Chang , Po-Han Lee , Hui-Hsien Wu , Jyun-Liang Wu
CPC classification number: H01L21/561 , G06K9/0004 , H01L21/6836 , H01L21/78 , H01L23/3114 , H01L23/481 , H01L2224/16225
Abstract: A chip package includes a chip, a first adhesive layer, a second adhesive layer, and a protection cap. The chip has a sensing area, a first surface, a second surface that is opposite to the first surface, and a side surface adjacent to the first and second surfaces. The sensing area is located on the first surface. The first adhesive layer covers the first surface of the chip. The second adhesive layer is located on the first adhesive layer, such that the first adhesive layer is between the first surface and the second adhesive layer. The protection cap has a bottom board and a sidewall that surrounds the bottom board. The bottom board covers the second adhesive layer, and the sidewall covers the side surface of the chip.
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