公开(公告)号：US20140015111A1

公开(公告)日：2014-01-16

申请号：US13941854

申请日：2013-07-15

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Shih-Chin CHEN ,  Yi-Ming CHANG ,  Chien-Hui CHEN ,  Chia-Ming CHENG ,  Wei-Luen SUEN ,  Chen-Han CHIANG

IPC: H01L23/544 ,  H01L21/78

CPC classification number: H01L23/544 ,  H01L21/78 ,  H01L23/3185 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/5446 ,  H01L2224/02371 ,  H01L2224/02377 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/05569 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05669 ,  H01L2224/06155 ,  H01L2224/0616 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/14155 ,  H01L2224/1416 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05552

Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and an opposite second surface; a device region disposed in the substrate; a dielectric layer located on the first surface of the semiconductor substrate; a plurality of conducting pads located in the dielectric layer and electrically connected to the device region; at least one alignment mark disposed in the semiconductor substrate and extending from the second surface towards the first surface.

Abstract translation: 本发明的实施例提供一种芯片封装，其包括：具有第一表面和相对的第二表面的半导体衬底; 设置在所述基板中的装置区域; 位于半导体衬底的第一表面上的电介质层; 位于所述电介质层中并电连接到所述器件区域的多个导电焊盘; 设置在所述半导体衬底中并且从所述第二表面朝向所述第一表面延伸的至少一个对准标记。

公开(公告)号：US20130341747A1

公开(公告)日：2013-12-26

申请号：US13921999

申请日：2013-06-19

Applicant: XINTEC INC.

Inventor： Po-Shen LIN ,  Tsang-Yu LIU ,  Yen-Shih HO ,  Chih-Wei HO ,  Shih-Chin CHEN

IPC: H01L31/0232 ,  H01L31/02

CPC classification number: H01L31/0232 ,  H01L23/3114 ,  H01L27/14618 ,  H01L31/02 ,  H01L31/02327 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An embodiment of the invention provides a chip package which includes: a chip including: a semiconductor substrate having a first surface; a device region formed in the semiconductor substrate; and a plurality of micro-lenses on the first surface and the device region; a cover substrate disposed on the chip, wherein the cover substrate is a transparent substrate; a spacer layer disposed between the chip and the cover substrate, wherein the spacer layer, the chip, and the cover substrate collectively surround a cavity in the device region; and at least one main lens on the cover substrate and in the cavity, wherein a width of the main lens is greater than that of each of the micro-lenses.

Abstract translation: 本发明的实施例提供一种芯片封装，其包括：芯片，包括：具有第一表面的半导体衬底; 形成在所述半导体衬底中的器件区域; 以及在所述第一表面和所述器件区域上的多个微透镜; 设置在所述芯片上的盖基板，其中所述盖基板为透明基板; 设置在所述芯片和所述覆盖基板之间的间隔层，其中所述间隔层，所述芯片和所述覆盖基板一起围绕所述器件区域中的空腔; 以及在所述盖基板上和所述空腔中的至少一个主透镜，其中所述主透镜的宽度大于每个所述微透镜的宽度。