公开(公告)号：US20240321800A1

公开(公告)日：2024-09-26

申请号：US18444786

申请日：2024-02-19

申请人： E Ink Holdings Inc.

发明人： Wenchuan Wang ,  Kuang-Heng Liang ,  Wen-Yu Kuo ,  Yen-Ze Huang ,  Jen-Shiun Huang

IPC分类号： H01L23/00 ,  G02B26/00 ,  G02F1/167 ,  G02F1/1676 ,  G02F1/1677

CPC分类号： H01L24/16 ,  G02B26/005 ,  G02F1/1676 ,  G02F1/1677 ,  H01L24/05 ,  H01L24/13 ,  G02F1/167 ,  H01L24/14 ,  H01L2224/05541 ,  H01L2224/05555 ,  H01L2224/13007 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/14051 ,  H01L2224/14155 ,  H01L2224/16237 ,  H01L2924/1426

摘要： A display device includes a driving circuit substrate, a display layer, an opposite substrate, and a conducting structure. The driving circuit substrate includes a first substrate and a driving circuit layer disposed on the first substrate. The driving circuit layer includes a display region, a peripheral region at the periphery of the display region, and a conducting pad located between the peripheral region and an edge of the first substrate. The opposite substrate includes a second substrate and an opposite electrode layer disposed on the second substrate. The display layer is located between the opposite electrode layer and the driving circuit layer. A conductive member of the conducting structure is connected between the conducting pad and the opposite electrode layer. The conducting structure has a first width. The peripheral region has a second width. The first width is less than or equal to 2.5 times the second width.

公开(公告)号：US09818678B2

公开(公告)日：2017-11-14

申请号：US14222649

申请日：2014-03-23

申请人： Renesas Electronics Corporation

发明人： Jumpei Konno ,  Takafumi Nishita ,  Nobuhiro Kinoshita ,  Kazunori Hasegawa ,  Michiaki Sugiyama

IPC分类号： H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01L21/683 ,  H01L21/56

CPC分类号： H01L23/49811 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/6836 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/81 ,  H01L24/85 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/05554 ,  H01L2224/10175 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/136 ,  H01L2224/14153 ,  H01L2224/14155 ,  H01L2224/1601 ,  H01L2224/16105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/81385 ,  H01L2224/814 ,  H01L2224/81444 ,  H01L2224/83102 ,  H01L2224/85 ,  H01L2224/85203 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2924/00 ,  H01L2224/48

摘要： To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width W1 and a narrow part (a second portion) with a second width W2. When the solder material is heated, the thickness of the solder material arranged over the narrow part becomes smaller than the thickness of the solder material arranged in the wide part. Then, in the flip-chip bonding step, a projecting electrode is arranged over the narrow part and bonded onto the narrow part. Thus, the amount of protrusion of the solder material can be reduced.

公开(公告)号：US09806060B2

公开(公告)日：2017-10-31

申请号：US15431110

申请日：2017-02-13

申请人： SK hynix Inc.

发明人： Chan Woo Jeong

IPC分类号： H01L25/065 ,  H01L23/31 ,  H01L23/28 ,  H01L23/29 ,  H01L23/08 ,  H01L23/00 ,  H01L23/498

CPC分类号： H01L25/0652 ,  H01L23/08 ,  H01L23/293 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/4985 ,  H01L23/562 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06155 ,  H01L2224/13294 ,  H01L2224/133 ,  H01L2224/14155 ,  H01L2224/14165 ,  H01L2224/16145 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/73207 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/1015 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099

摘要： A flexible package may be provided. The flexible package may include a flexible molding member including a top surface. The flexible package may include a first chip within the flexible molding member, and including a first top surface. The flexible package may include a second chip within the flexible molding member, and including a second top surface. The first top surface may face away from the top surface of the flexible molding member and the second top surface may face towards the top surface of the flexible molding member.

公开(公告)号：US20170062322A1

公开(公告)日：2017-03-02

申请号：US15207559

申请日：2016-07-12

申请人： Renesas Electronics Corporation

发明人： Kazuyuki SAKATA ,  Takafumi BETSUI

IPC分类号： H01L23/498 ,  H01L23/00

CPC分类号： H01L23/49838 ,  H01L21/563 ,  H01L22/32 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/06133 ,  H01L2224/06136 ,  H01L2224/06155 ,  H01L2224/06177 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/14133 ,  H01L2224/14136 ,  H01L2224/14155 ,  H01L2224/16238 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/49173 ,  H01L2224/49175 ,  H01L2224/49179 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/45099

摘要： A semiconductor device with enhanced reliability. The semiconductor device has a wiring substrate which includes a first terminal electrically connected with a power supply potential supply section of a semiconductor chip, a first wiring coupling the power supply potential supply section with the first terminal, a second terminal electrically connected with a reference potential supply section of the semiconductor chip, and a second wiring coupling the reference potential supply section with the second terminal. The first terminal and second terminal are arranged closer to the periphery of the wiring substrate than the semiconductor chip. The second wiring is extended along the first wiring.

摘要翻译： 具有增强可靠性的半导体器件。 半导体器件具有布线基板，其包括与半导体芯片的电源电位供给部电连接的第一端子，将电源电位供给部与第一端子连接的第一布线，与基准电位电连接的第二端子 半导体芯片的供电部分和将参考电位供应部分与第二端子耦合的第二布线。 第一端子和第二端子比半导体芯片更靠近布线基板的周边布置。 第二个接线沿着第一个接线延伸。

公开(公告)号：US09524946B2

公开(公告)日：2016-12-20

申请号：US14466021

申请日：2014-08-22

申请人： Murata Manufacturing Co., Ltd.

发明人： Katsumi Ishii ,  Masashi Yamaura

IPC分类号： H01L23/00 ,  H01L23/498

CPC分类号： H01L24/14 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/10165 ,  H01L2224/10175 ,  H01L2224/13005 ,  H01L2224/13014 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14155 ,  H01L2224/1601 ,  H01L2224/16058 ,  H01L2224/16238 ,  H01L2224/17519 ,  H01L2224/8114 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/81444 ,  H01L2924/1305 ,  H01L2924/15787 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/206

摘要： An electronic device includes a surface-mounted component and a mounting component on which the surface-mounted component is mounted, the surface-mounted component includes a first bump and a second bump, a cross-sectional area of which in an in-plane direction of a surface facing the mounting component is larger than that of the first bump, on the surface facing the mounting component, the mounting component includes a first pad that is soldered to the first bump and a second pad soldered to the second bump on the surface facing the surface-mounted component, and a ratio of an area of the second pad to the cross-sectional area of the second bump is larger than a ratio of an area of the first pad to the cross-sectional area of the first bump.

摘要翻译： 电子设备包括表面安装部件和安装在其上的表面安装部件的安装部件，表面安装部件包括第一凸块和第二凸块，其横截面积在面内方向上 面向安装部件的表面的尺寸大于第一凸块的表面，在面向安装部件的表面上，安装部件包括焊接到第一凸块的第一焊盘和焊接到表面上的第二凸起的第二焊盘 面对所述表面安装部件，并且所述第二焊盘的面积与所述第二凸起的横截面面积的比率大于所述第一焊盘的面积与所述第一凸块的横截面面积的比率。

公开(公告)号：US20160365328A1

公开(公告)日：2016-12-15

申请号：US14736943

申请日：2015-06-11

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Richard S. GRAF ,  Jay F. LEONARD ,  David J. WEST ,  Charles H. WILSON

IPC分类号： H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L21/56

CPC分类号： H01L24/17 ,  H01L21/563 ,  H01L23/562 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/11332 ,  H01L2224/11442 ,  H01L2224/11505 ,  H01L2224/11552 ,  H01L2224/1181 ,  H01L2224/11901 ,  H01L2224/13005 ,  H01L2224/13017 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/13184 ,  H01L2224/14135 ,  H01L2224/14155 ,  H01L2224/16059 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/17104 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/81986 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06568 ,  H01L2924/20645 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/00012

摘要： Sintered connection structures and methods of manufacture are disclosed. The method includes placing a powder on a substrate and sintering the powder to form a plurality of pillars. The method further includes repeating the placing and sintering steps until the plurality of pillars reach a predetermined height. The method further includes forming a solder cap on the plurality of pillars. The method further includes joining the substrate to a board using the solder cap.

公开(公告)号：US09443809B2

公开(公告)日：2016-09-13

申请号：US14732086

申请日：2015-06-05

申请人： uPI semiconductor corp.

发明人： Chau-Chun Wen ,  Hsing-Wu Li

IPC分类号： H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/492 ,  H01L23/58 ,  H01L21/60

CPC分类号： H01L23/562 ,  H01L21/56 ,  H01L23/3171 ,  H01L23/492 ,  H01L23/585 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L2021/6027 ,  H01L2224/0401 ,  H01L2224/05014 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05554 ,  H01L2224/05568 ,  H01L2224/0558 ,  H01L2224/06155 ,  H01L2224/08113 ,  H01L2224/13023 ,  H01L2224/13027 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13164 ,  H01L2224/14155 ,  H01L2224/16227 ,  H01L2224/32104 ,  H01L2224/32221 ,  H01L2224/81193 ,  H01L2924/00014 ,  H01L2924/014

摘要： A portable apparatus, an IC packaging structure, an IC packaging object, and an IC packaging method thereof are disclosed. The IC packaging structure includes an IC packaging object and a substrate. The packaging object includes a die and a metallurgy layer. The die has a contact portion, a saw reserved portion, and a seal ring. The seal ring is disposed between the contact portion and the saw reserved portion. The metallurgy layer is disposed on the contact portion. At least a part of the metallurgy layer overlaps the seal ring. The metallurgy layer includes a solderable layer coated by a solder paste. The substrate includes a solder pad. The solder pad is coupled to the solderable layer coated by the solder paste.

摘要翻译： 公开了便携式设备，IC封装结构，IC封装物体及其IC封装方法。 IC封装结构包括IC封装体和基板。 包装对象包括模具和冶金层。 模具具有接触部分，锯片预留部分和密封环。 密封环设置在接触部分和锯保留部分之间。 冶金层设置在接触部分上。 冶金层的至少一部分与密封圈重叠。 冶金层包括用焊膏涂覆的可焊层。 衬底包括焊盘。 焊料焊盘与由焊膏涂覆的可焊层相连。

公开(公告)号：US20160111388A1

公开(公告)日：2016-04-21

申请号：US14983753

申请日：2015-12-30

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Shinji Baba ,  Masaki Watanabe ,  Muneharu Tokunaga ,  Kazuyuki Nakagawa

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L23/29 ,  H01L23/498

CPC分类号： H01L24/17 ,  H01L21/563 ,  H01L23/291 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/3171 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/1134 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13075 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/14136 ,  H01L2224/14155 ,  H01L2224/14177 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

摘要： A technique capable of improving reliability of a semiconductor device is provided. In the present invention, as a wiring board on which a semiconductor chip is mounted, a build-up wiring board is not used but a through wiring board THWB is used. In this manner, in the present invention, the through wiring board formed of only a core layer is used, so that it is not required to consider a difference in thermal expansion coefficient between a build-up layer and the core layer, and besides, it is not required either to consider the electrical disconnection of a fine via formed in the build-up layer because the build-up layer does not exist. As a result, according to the present invention, the reliability of the semiconductor device can be improved while a cost is reduced.

摘要翻译： 提供了能够提高半导体器件的可靠性的技术。 在本发明中，作为安装有半导体芯片的布线基板，不使用积层布线板，而是使用贯通布线板THWB。 以这种方式，在本发明中，仅使用芯层形成的贯通布线板，因此不需要考虑堆积层与芯层之间的热膨胀系数的差异， 不需要考虑由于积聚层不存在而在积层中形成的精细通孔的电断开。 结果，根据本发明，可以提高半导体器件的可靠性，同时降低成本。

公开(公告)号：US20160086931A1

公开(公告)日：2016-03-24

申请号：US14957567

申请日：2015-12-02

申请人： Chul-yong JANG ,  Young-lyong KIM ,  Ae-nee JANG

发明人： Chul-yong JANG ,  Young-lyong KIM ,  Ae-nee JANG

IPC分类号： H01L25/00 ,  H01L23/00 ,  H01L21/48

CPC分类号： H01L25/0657 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/27 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/96 ,  H01L25/50 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/14155 ,  H01L2224/16058 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/2746 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2224/8203 ,  H01L2224/92244 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/83 ,  H01L2224/11 ,  H01L2924/00 ,  H01L2924/00012

摘要： Embodiments of the inventive concept include a semiconductor package having a plurality of stacked semiconductor chips. A multi-layered substrate includes a central insulation layer, an upper wiring layer disposed on an upper surface of the central insulation layer, and a first lower wiring layer disposed on a lower surface of the central insulation layer. The stacked semiconductor chips are connected to the multi-layered substrate and/or each other using various means. The semiconductor package is capable of high performance operation, like a semiconductor package based on flip-ship bonding, and also meets the need for large capacity by overcoming a limitation caused by a single semiconductor chip. Embodiments of the inventive concept also include methods of manufacturing the semiconductor package.

公开(公告)号：US20160027742A1

公开(公告)日：2016-01-28

申请号：US14732086

申请日：2015-06-05

申请人： uPI semiconductor corp.

发明人： Chau-Chun Wen ,  Hsing-Wu Li

IPC分类号： H01L23/00

CPC分类号： H01L23/562 ,  H01L21/56 ,  H01L23/3171 ,  H01L23/492 ,  H01L23/585 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L2021/6027 ,  H01L2224/0401 ,  H01L2224/05014 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05554 ,  H01L2224/05568 ,  H01L2224/0558 ,  H01L2224/06155 ,  H01L2224/08113 ,  H01L2224/13023 ,  H01L2224/13027 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13164 ,  H01L2224/14155 ,  H01L2224/16227 ,  H01L2224/32104 ,  H01L2224/32221 ,  H01L2224/81193 ,  H01L2924/00014 ,  H01L2924/014

摘要： A portable apparatus, an IC packaging structure, an IC packaging object, and an IC packaging method thereof are disclosed. The IC packaging structure includes an IC packaging object and a substrate. The packaging object includes a die and a metallurgy layer. The die has a contact portion, a saw reserved portion, and a seal ring. The seal ring is disposed between the contact portion and the saw reserved portion. The metallurgy layer is disposed on the contact portion. At least a part of the metallurgy layer overlaps the seal ring. The metallurgy layer includes a solderable layer coated by a solder paste. The substrate includes a solder pad. The solder pad is coupled to the solderable layer coated by the solder paste.

摘要翻译： 公开了便携式设备，IC封装结构，IC封装物体及其IC封装方法。 IC封装结构包括IC封装体和基板。 包装对象包括模具和冶金层。 模具具有接触部分，锯片预留部分和密封环。 密封环设置在接触部分和锯保留部分之间。 冶金层设置在接触部分上。 冶金层的至少一部分与密封圈重叠。 冶金层包括用焊膏涂覆的可焊层。 衬底包括焊盘。 焊料焊盘与由焊膏涂覆的可焊层相连。