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15 条记录 (耗时 0.014 秒)

    Resource management within a load store unit
    2.
    发明授权
    Resource management within a load store unit 有权
    加载存储单元内的资源管理

    公开(公告)号：US09047092B2

    公开(公告)日：2015-06-02

    申请号：US13724094

    申请日：2012-12-21

    申请人： ARM LIMITED

    发明人： Mélanie Emanuelle Lucie Teyssier ,  Philippe Pierre Maurice Luc ,  Albin Pierick Tonnerre

    IPC分类号： G06F9/38

    CPC分类号： G06F9/38 ,  G06F9/3824 ,  G06F9/3838 ,  G06F9/3855 ,  G06F2212/25

    摘要： A load store pipeline 18 includes an issue queue 20 and load store circuitry 24. The load store circuitry 24 includes the plurality of access slot circuits 26 to 40. Dependency tracking circuitry 42, 44, 46, 48 serves to track a freeable number of access slot circuits 26 to 42 corresponding to the sum of access slot circuits that are empty and those processing data access instructions which have not bypassed any preceding data access instructions within the program execution order.

    摘要翻译： 加载存储流水线18包括发布队列20和加载存储电路24.加载存储电路24包括多个访问时隙电路26至40.依赖性跟踪电路42,44,46,48用于跟踪可访问数量的访问 时隙电路26至42对应于空闲的接入时隙电路之和，以及处理数据访问指令，这些处理数据访问指令在程序执行顺序中没有绕过任何先前的数据访问指令。

    Methods for sustained read and write performance with non-volatile memory
    3.
    发明授权
    Methods for sustained read and write performance with non-volatile memory 有权
    使用非易失性存储器持续读写性能的方法

    公开(公告)号：US08949555B1

    公开(公告)日：2015-02-03

    申请号：US13162575

    申请日：2011-06-16

    申请人： Vijay Karamcheti ,  Shibabrata Mondal ,  Ajith Kumar

    发明人： Vijay Karamcheti ,  Shibabrata Mondal ,  Ajith Kumar

    IPC分类号： G06F12/00

    CPC分类号： G06F3/061 ,  G06F3/0655 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0246 ,  G06F12/0253 ,  G06F12/06 ,  G06F13/161 ,  G06F13/1626 ,  G06F13/1642 ,  G06F13/1657 ,  G06F13/1694 ,  G06F13/18 ,  G06F13/364 ,  G06F13/4081 ,  G06F13/4282 ,  G06F2212/25 ,  G06F2212/702 ,  G06F2212/7203 ,  G06F2212/7205

    摘要： In one embodiment of the invention, a memory system includes non-volatile-memory-devices (NVMDs) coupled to memory channels to share busses and a memory controller coupled to the memory channels in communication between the plurality of NVMDs. Each NVMD independently executes a read, write, or erase operation at a time. The memory controller includes channel schedulers to schedule control and data transfers associated with the read, write, and erase operations on the memory channels; and high priority and low priority queues coupled to the channel schedulers. The channel schedulers prioritize operations waiting in the high priority queues over operations waiting in the low priority queues. The channel schedulers further prioritize read operations waiting in either the high priority queue or the low priority queue over write and erase operations waiting in each respective queue.

    摘要翻译： 在本发明的一个实施例中，存储器系统包括耦合到存储器通道以共享总线的非易失性存储器件（NVMD）和耦合到多个NVMD之间的通信中的存储器通道的存储器控​​制器。 每个NVMD一次独立地执行读，写或擦除操作。 存储器控制器包括用于调度与存储器通道上的读取，写入和擦除操作相关联的控制和数据传输的信道调度器; 以及耦合到信道调度器的高优先级和低优先级队列。 信道调度器优先处理在高优先级队列中等待低优先级队列中的操作的操作。 信道调度器进一步优先考虑在高优先级队列或低优先级队列中等待在每个相应队列中等待的写入和擦除操作的读取操作。

    MEMORY CHANNEL CONNECTED NON-VOLATILE MEMORY
    4.
    发明申请
    MEMORY CHANNEL CONNECTED NON-VOLATILE MEMORY 有权
    内存通道连接的非易失性存储器

    公开(公告)号：US20140379969A1

    公开(公告)日：2014-12-25

    申请号：US14475398

    申请日：2014-09-02

    申请人： Virident Systems, Inc.

    发明人： Vijay Karamcheti ,  Kumar Ganapathy ,  Kenneth Alan Okin ,  Rajesh Parekh

    IPC分类号： G06F12/02

    CPC分类号： G06F12/0246 ,  G06F12/0638 ,  G06F13/12 ,  G06F13/1657 ,  G06F13/1694 ,  G06F2212/25 ,  G06F2212/7203 ,  G11C7/1006 ,  G11C7/1072 ,  Y02D10/14

    摘要： An apparatus includes a printed circuit board with a plurality of printed circuit board traces, a memory controller mounted on the printed circuit board coupled to one or more of the plurality of printed circuit board traces, a plurality of non-volatile type of memory integrated circuits coupled to the printed circuit board, and a plurality of support integrated circuits coupled between the memory controller and the plurality of non-volatile type of memory integrated circuits.

    摘要翻译： 一种装置包括具有多个印刷电路板迹线的印刷电路板，安装在与多个印刷电路板迹线中的一个或多个印刷电路板迹线耦合的印刷电路板上的存储器控​​制器，多个非易失型存储器集成电路 耦合到印刷电路板，以及耦合在存储器控制器和多个非易失性类型的存储器集成电路之间的多个支持集成电路。