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公开(公告)号：US10003414B2
公开(公告)日：2018-06-19
申请号：US15345811
申请日：2016-11-08
发明人： Arnaud Casagrande
IPC分类号： H04B1/38 , H04B17/11 , H04B17/21 , H03F3/195 , H03F3/24 , H03G3/30 , H03L7/089 , H03L7/091 , H03L7/099 , H03L7/185 , H03C3/09
CPC分类号： H04B17/11 , H03C3/0941 , H03C3/095 , H03C3/0975 , H03C3/0991 , H03F3/195 , H03F3/245 , H03F2200/294 , H03F2200/451 , H03G3/3047 , H03L7/0891 , H03L7/091 , H03L7/099 , H03L7/185 , H04B17/21
摘要： The method for calibrating the frequency synthesizer using two-point FSK modulation consists, in a first phase, in supplying an excitation signal generated by a calibration unit to a sigma-delta modulator by deactivating a digital-to-analog converter and transmitting the output signal from a loop filter of the synthesizer to the calibration unit, which digitally converts the incoming signal and offsets the phase shift between the excitation signal and the loop filter output signal in the calibration unit. In a second phase, the excitation signal is supplied to the sigma-delta modulator and to the activated digital-to-analog converter, and the digital-to-analog converter gain is calibrated by checking, in the calibration unit, the polarity of the loop filter output signal with respect to the excitation signal, and using a dichotomy algorithm.
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公开(公告)号：US20170141857A1
公开(公告)日：2017-05-18
申请号：US15345811
申请日：2016-11-08
发明人： Arnaud CASAGRANDE
IPC分类号： H04B17/11 , H03L7/099 , H03L7/089 , H04B17/21 , H03F3/195 , H03F3/24 , H03G3/30 , H03L7/185 , H03L7/091
CPC分类号： H04B17/11 , H03C3/0941 , H03C3/095 , H03C3/0975 , H03C3/0991 , H03F3/195 , H03F3/245 , H03F2200/294 , H03F2200/451 , H03G3/3047 , H03L7/0891 , H03L7/091 , H03L7/099 , H03L7/185 , H04B17/21
摘要： The method for calibrating the frequency synthesiser using two-point FSK modulation consists, in a first phase, in supplying an excitation signal generated by a calibration unit to a sigma-delta modulator by deactivating a digital-to-analogue converter and transmitting the output signal from a loop filter of the synthesiser to the calibration unit, which digitally converts the incoming signal and offsets the phase shift between the excitation signal and the loop filter output signal in the calibration unit. In a second phase, the excitation signal is supplied to the sigma-delta modulator and to the activated digital-to-analogue converter, and the digital-to-analogue converter gain is calibrated by checking, in the calibration unit, the polarity of the loop filter output signal with respect to the excitation signal, and using a dichotomy algorithm.
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公开(公告)号：US20160269171A1
公开(公告)日：2016-09-15
申请号：US14844977
申请日：2015-09-03
发明人： Hiroki SAKURAI
CPC分类号： H03L7/0991 , H03C3/0925 , H03C3/0933 , H03C3/0941 , H03C3/095 , H03C3/0966 , H03C3/0975 , H03L7/0802 , H03L7/087 , H03L7/093 , H03L2207/50
摘要： According to one embodiment, a radio communication device includes PLL circuit that adjusts, based on control data, a frequency of an output signal to a target value, a holder that temporarily holds, when a hold instruction signal to hold the control data is input, a state of the control data and releases, when an unhold instruction signal to unhold the control data is input, a holding state of the control data, a control unit that outputs the hold instruction signal in a PLL lock state in which the frequency of the output signal reaches the target value, and outputs the unhold instruction signal after the hold instruction signal is output and before the frequency of the output signal deviates from the target value or a vicinity of the target value.
摘要翻译： 根据一个实施例，无线电通信装置包括PLL电路，PLL电路基于控制数据将输出信号的频率调整为目标值，当输入保持控制数据的保持指令信号时暂时保持的持有者， 控制数据的状态，当输入取消保持控制数据的未保持指令信号时，释放控制数据的保持状态，在PLL锁定状态下输出保持指示信号的控制单元，其中， 输出信号达到目标值，并且在保持指令信号输出之后并且在输出信号的频率偏离目标值或目标值附近之前输出未保持指令信号。
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公开(公告)号：US09300307B2
公开(公告)日：2016-03-29
申请号：US14616192
申请日：2015-02-06
申请人： DUST NETWORKS, INC.
CPC分类号： H03L7/18 , H03C3/0925 , H03C3/0933 , H03C3/0941 , H03C3/0966 , H03C3/0975 , H03K3/0315 , H03L7/0814
摘要： A frequency synthesizer directly generates phase modulated radio-frequency (RF) signals. The frequency synthesizer includes a voltage controlled oscillator (VCO) producing a synthesized frequency signal having a frequency controlled based on a signal received at an input of the VCO. A digitally adjustable frequency divider produces a reduced frequency signal from the synthesized frequency signal. A phase digital-to-analog converter (DAC) produces a delayed version of a timing signal (e.g., the reduced frequency signal, or a reference clock signal) that is delayed according to a digital control signal. A phase detector (PD) produces a phase control signal from the reduced frequency signal and/or the delayed timing signal. A digital signal converter controls the digitally adjustable frequency divider and the phase DAC so as to cause a phase or frequency of the synthesized frequency signal output by the VCO to track a desired phase or frequency trajectory encoded in a digital signal.
摘要翻译： 频率合成器直接产生相位调制的射频（RF）信号。 频率合成器包括压控振荡器（VCO），其产生具有基于在VCO的输入处接收的信号的频率控制的合成频率信号。 数字可调分频器产生来自合成频率信号的降频信号。 相位数/模转换器（DAC）产生根据数字控制信号延迟的定时信号（例如，降频信号或参考时钟信号）的延迟版本。 相位检测器（PD）从降频信号和/或延迟定时信号产生相位控制信号。 数字信号转换器控制数字可调分频器和相位DAC，以使由VCO输出的合成频率信号的相位或频率跟踪以数字信号编码的所需相位或频率轨迹。
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公开(公告)号：US20150263670A1
公开(公告)日：2015-09-17
申请号：US14203572
申请日：2014-03-11
发明人： Yiping Fan , Chun-Yuan Lin , Sheng-Wei Chiang , Yi-Chun Lu
IPC分类号： H03B5/12
CPC分类号： H03B5/1206 , H03B5/1228 , H03B5/1243 , H03C3/0916 , H03C3/0941 , H03C3/0958 , H03C3/0975
摘要： A two path direct frequency modulation system is disclosed. The system includes a Varactor, a voltage-controlled oscillator (VCO) calibration capacitor bank including a first plurality of switchable capacitors, and a frequency deviation capacitor bank including a second plurality of switchable capacitors. The method includes switching on or off a number of the first plurality of switchable capacitors to obtain a desired frequency band and determining number of cycles within a first predetermined time to obtain a first count, switching on or off a number of the first plurality of switchable capacitors or of the second plurality of switchable capacitors to change the desired frequency band and determining number of cycles within a second predetermined time to obtain a second count, and modulating a data signal by switching on or off a switchable capacitors of the second plurality of switchable capacitors according to the first and the second count.
摘要翻译： 公开了一种双路直接调频系统。 该系统包括Varactor，包括第一多个可切换电容器的压控振荡器（VCO）校准电容器组，以及包括第二多个可切换电容器的频偏电容器组。 该方法包括：接通或关闭第一多个可切换电容器的数量以获得期望的频带，并且确定在第一预定时间内的周期数以获得第一计数，接通或关闭第一多个可切换电容器 电容器或第二多个可切换电容器，以改变期望的频带并确定在第二预定时间内的周期数以获得第二计数，以及通过接通或关闭第二多个可切换电容器的可切换电容器来调制数据信号 电容器根据第一和第二计数。
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6.发明申请TRANSCEIVER USING TECHNIQUE FOR IMPROVEMENT OF PHASE NOISE AND SWITCHING OF PHASE LOCK LOOP (PLL) 有权收发器使用技术改进相位噪声和相位锁定环路（PLL）的切换公开(公告)号：US20130316661A1
公开(公告)日：2013-11-28
申请号：US13891474
申请日：2013-05-10
发明人： Jaesup LEE , Hong Jin KIM , Hyung Gu PARK , Kang Yoon LEE
IPC分类号： H03C3/09
CPC分类号： H04B1/38 , H03B5/1215 , H03B5/1228 , H03B2200/0062 , H03C3/0916 , H03C3/0975 , H03C3/0991 , H03L7/0802 , H03L7/0895 , H03L7/0898 , H03L7/099 , H03L7/1072 , H04L5/0062 , H04L7/033 , H04L2027/0016 , H04L2027/0022 , H04L2027/0055
摘要： A transceiver may include a reception (Rx) radio frequency (RF) part configured to process a received signal, a transmission (Tx) RF part configured to process a transmitted signal, and a phase lock loop (PLL) configured to provide a reception frequency to the reception RF part and provide a transmission frequency to the transmission RF part. The PLL may be controlled according to whether the reception RF part or the transmission RF part is on. In addition, a transceiver may include quenching waveform generator (QWGs) to control quenching waveforms of the RF parts corresponding to a plurality of antennas. The quenching waveforms may be generated respectively by VCOs operating at a same frequency. The QWGs may control the VCOs such that the quenching waveforms do not overlap.
摘要翻译： 收发器可以包括被配置为处理接收信号的接收（Rx）射频（RF）部分，被配置为处理发送信号的发送（Tx）RF部分）和被配置为提供接收频率 并且向发送RF部提供发送频率。 PLL可以根据接收RF部分还是发射RF部分接通来控制。 此外，收发器可以包括淬火波形发生器（QWG）以控制对应于多个天线的RF部件的淬灭波形。 淬灭波形可以由以相同频率工作的VCO分别产生。 QWG可以控制VCO，使得淬灭波形不重叠。
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7.发明授权公开(公告)号：US07979037B2
公开(公告)日：2011-07-12
申请号：US11878286
申请日：2007-07-23
申请人： Toru Matsuura
发明人： Toru Matsuura
IPC分类号： H04B1/04
CPC分类号： H03C3/0941 , H03C3/095 , H03C3/0975
摘要： A bandpass type delta sigma modulation section performs delta sigma modulation on an inputted modulation signal such that quantization noise is reduced in a frequency band which requires low noise. A low pass filter removes a noise component in a high frequency region from the signal on which the delta sigma modulation has been performed. A frequency modulation circuit reduces noise in the frequency band which requires low noise with the bandpass type delta sigma modulation section and the low pass filter, and reduces noise in the vicinity of a direct current component DC with a feedback comparison section and a loop filter.
摘要翻译： 带通型ΔΣ调制部分对输入的调制信号执行ΔΣ调制，使得量化噪声在需要低噪声的频带中减小。 低通滤波器从已经执行了Δ-Σ调制的信号中去除高频区域中的噪声分量。 频率调制电路通过带通型ΔΣ调制部分和低通滤波器降低需要低噪声的频带中的噪声，并且通过反馈比较部分和环路滤波器降低直流分量DC附近的噪声。
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公开(公告)号：US20100203852A1
公开(公告)日：2010-08-12
申请号：US12762601
申请日：2010-04-19
申请人： Toru MATSUURA
发明人： Toru MATSUURA
IPC分类号： H04B1/04
CPC分类号： H03C3/0941 , H03C3/095 , H03C3/0975
摘要： A bandpass type delta sigma modulation section 15 performs delta sigma modulation on an inputted modulation signal such that quantization noise is reduced in a frequency band which requires low noise. An LPF 16 removes a noise component in a high frequency region from the signal on which the delta sigma modulation has been performed. A frequency modulation circuit 1 reduces noise in the frequency band which requires low noise with the bandpass type delta sigma modulation section 15 and the LPF 16, and reduces noise in the vicinity of a direct current component DC with a feedback comparison section 11 and a loop filter 12.
摘要翻译： 带通型ΔΣ调制部分15对输入的调制信号执行ΔΣ调制，使得量化噪声在需要低噪声的频带中减小。 LPF16从已经执行了ΔΣ调制的信号中去除高频区域中的噪声分量。 频率调制电路1通过带通型ΔΣ调制部分15和LPF 16降低需要低噪声的频带中的噪声，并且通过反馈比较部分11和环路减小直流分量DC附近的噪声 过滤器12。
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公开(公告)号：US20080266015A1
公开(公告)日：2008-10-30
申请号：US12090727
申请日：2006-10-18
IPC分类号： H03C5/00
CPC分类号： H03C3/0941 , H03C3/095 , H03C3/0975 , H03C5/00 , H04L27/361
摘要： The present invention relates to a polar modulation apparatus and method, in which an in-phase and a quadrature-phase signal are processed in the analog domain to generate an analog signal corresponding to a derivative of a phase component of said polar-modulated signal. The analog signal is then input to a control input of a controlled oscillator (40). As an example, the processing may be based on a differentiate-and-multiply algorithm in the analog domain. Thereby, phase and envelope signals are generated in the analog domain and bandwidth enlargement due to the processing of the polar signals and corresponding aliasing can be prevented to obtain a highly accurate polar-modulated output signal.
摘要翻译： 本发明涉及一种极坐标调制装置和方法，其中在模拟域中处理同相和正交相位信号以产生对应于所述极坐标调制信号的相位分量的微分的模拟信号。 然后将模拟信号输入到受控振荡器（40）的控制输入端。 作为示例，处理可以基于模拟域中的差分和乘法算法。 因此，在模拟域中产生相位和包络信号，并且由于极坐标信号的处理而导致带宽放大，可以防止相应的混叠，从而获得高精度的极调制输出信号。
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10.发明授权公开(公告)号：US07292107B2
公开(公告)日：2007-11-06
申请号：US11163356
申请日：2005-10-17
申请人： Chao-Chih Hsiao , Min-Chieh Hsu , Ping-Hsun Hsieh
发明人： Chao-Chih Hsiao , Min-Chieh Hsu , Ping-Hsun Hsieh
CPC分类号： H03C3/0925 , H03C3/0941 , H03C3/0966 , H03C3/0975
摘要： A modulation method and a modulation apparatus in a phase-locked loop (PLL) provided. The modulation apparatus comprises a modulator, a crystal oscillator, a controllable R-divisor frequency divider, a controllable N-divisor frequency divider and a voltage-controlled oscillator (VCO). The crystal oscillator generates a fixed frequency oscillating signal. The controllable R-divisor frequency divider receives the oscillating signal from the crystal oscillator and divides the frequency by R. The VCO generates a frequency signal based on a voltage-controlled signal provided by the PLL and feedbacks the frequency signal to the controllable N-divisor frequency divider. The controller N-divisor frequency divider receives a feedback frequency from the VCO and divides the frequency by N. A PLL unit used to compare a frequency provided by the crystal oscillator and passed through the controllable R-divisor frequency divider, with a frequency provided by the VCO and passed through the controllable N-divisor frequency divider, for performing a phase-locked operation.
摘要翻译： 提供了锁相环（PLL）中的调制方法和调制装置。 调制装置包括调制器，晶体振荡器，可控R因数分频器，可控N因数分频器和压控振荡器（VCO）。 晶体振荡器产生固定频率振荡信号。 可控R因数分频器接收来自晶体振荡器的振荡信号，并将频率除以R. VCO产生基于由PLL提供的电压控制信号的频率信号，并将频率信号反馈到可控N因数 分频器 控制器N除数分频器从VCO接收反馈频率并将频率除以N.用于比较由晶体振荡器提供的频率并通过可控R因数分频器的频率的PLL单元，频率由 VCO并通过可控N因数分频器，用于执行锁相操作。
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