公开(公告)号：US5665634A

公开(公告)日：1997-09-09

申请号：US463560

申请日：1995-06-05

申请人： James D. Beasom

发明人： James D. Beasom

IPC分类号： H01L23/31 ,  H01L23/522 ,  H01L29/06 ,  H01L29/40 ,  H01L21/283 ,  H01L21/31

CPC分类号： H01L29/408 ,  H01L23/3192 ,  H01L23/5222 ,  H01L2924/0002 ,  Y10S148/013

摘要： In a semiconductor island structure with passive side isolation, a method and structure for reducing corner breakdown where a device conductor crosses the edge of the island. The decrease in the field strength at the island edge between the conductor and the adjacent conducting region may be achieved by increasing the depth of the insulator beneath the conductor where it crosses the island edge without the necessity for increasing the thickness of the layer of insulation applied directly to the surface of the island by the use of a second or higher level interconnect, e.g., the conventional deposition of one or more additional layers of insulation over the device terminal to increase the spacing between the conductor and the surface of the island. In this way the process by which the device is constructed may remain unchanged. The decrease in the field strength at the island edge may alternatively or in addition be achieved by increasing the thickness of the insulator providing lateral isolation without increasing the thickness of the substrate isolation by the use of lateral trench isolation formed independently of the substrate isolation.

摘要翻译： 在具有无源侧隔离的半导体岛结构中，用于减少器件导体跨越岛边缘的拐角击穿的方法和结构。 导体和相邻导电区域之间的岛边缘处的场强的减小可以通过增加导体下方的绝缘体的深度而越过岛边缘而实现，而不需要增加施加的绝缘层的厚度 通过使用第二或更高级别的互连（例如，在器件端子上常规沉积一个或多个额外的绝缘层）以增加导体和岛的表面之间的间隔直接到岛的表面。 以这种方式，构造装置的过程可以保持不变。 另外还可以通过增加提供横向隔离的绝缘体的厚度来实现岛边缘处的场强的降低，而不需要通过使用独立于衬底隔离而形成的侧向沟槽隔离来增加衬底隔离的厚度。

公开(公告)号：US5120669A

公开(公告)日：1992-06-09

申请号：US651460

申请日：1991-02-06

申请人： Gregory A. Schrantz

发明人： Gregory A. Schrantz

IPC分类号： H01L21/337 ,  H01L29/808

CPC分类号： H01L29/66901 ,  H01L29/808 ,  Y10S148/013 ,  Y10S148/106

摘要： An ion-implanted JFET has a channel barrier region at the top gate surface self-aligned to the source and drain, thereby maintaining sufficient separation between the channel barrier and the source and drain for attaining a high source/drain breakdown voltage. After a top gate and an underlying channel layer are ion-implanted through a thin oxide layer, a first photoresist layer is formed and patterned to expose surface portions of the thin oxide layer where source, drain and channel barrier regions are to be formed. Through these apertures in the first photoresist mask, shallow high impurity concentration surface region are ion-implanted. A second photoresist layer is formed on the first photoresist layer, and patterned to completely expose the first and second apertures in the first photoresist layer and to remove material of the second photoresistor layer down to the surface of the the oxide layer, while masking the barrier region. Source and drain regions are then implanted through the second photoresist layer and the exposed first and second apertures of the first mask. The dose and implantation energy is such that the second implant effectively overrides the shallow regions of the first implant. Because the locations at which the source and drain regions in the underlying semiconductor material are formed are defined by the pattern in the first photoresist mask, the source and drain regions are self-aligned with the barrier region.

摘要翻译： 离子注入的JFET在顶栅表面处具有与源极和漏极自对准的沟道势垒区域，从而在沟道势垒和源极和漏极之间保持足够的间隔，以获得高的源/漏击穿电压。 在通过薄氧化物层离子注入顶栅和下层通道层之后，形成第一光致抗蚀剂层并图案化以暴露将要形成源极，漏极和沟道势垒区的薄氧化物层的表面部分。 通过第一光致抗蚀剂掩模中的这些孔，离子注入浅的高杂质浓度表面区域。 在第一光致抗蚀剂层上形成第二光致抗蚀剂层，并且被图案化以完全暴露第一光致抗蚀剂层中的第一和第二孔，并且将第二光敏电阻层的材料向下移动到氧化物层的表面，同时掩蔽屏障 地区。 然后通过第二光致抗蚀剂层和第一掩模的暴露的第一和第二孔注入源区和漏区。 剂量和注入能量使得第二植入物有效地覆盖第一植入物的浅区域。 由于形成底层半导体材料中的源区和漏区的位置由第一光致抗蚀剂掩模中的图案限定，源区和漏区与屏障区域自对准。

公开(公告)号：US5408125A

公开(公告)日：1995-04-18

申请号：US177299

申请日：1994-01-04

申请人： John P. Erdeljac ,  Louis N. Hutter

发明人： John P. Erdeljac ,  Louis N. Hutter

IPC分类号： H01L21/8249 ,  H01L27/04

CPC分类号： H01L21/8249 ,  Y10S148/013 ,  Y10S257/917 ,  Y10S257/929

摘要： A method of manufacturing semiconductor devices with increased operating voltages is described. A dopant of a second conductivity type is implanted into a region of a first epitaxial layer of the first conductivity type to form a buried layer. A substantially smaller dosage of a faster-diffusing dopant of the second conductivity type is then implanted into the buried layer region. The second epitaxial layer of the first conductivity type is formed over the first epitaxial layer. A region of the second epitaxial layer overlying the doped region of the first epitaxial layer is implanted with a dopant of the second conductivity type and diffused to form a doped well. The faster-diffusing dopant diffuses upward to make good electrical contact with the doped well diffusing downward from the surface. The lateral diffusion of the faster-diffusing dopant can be contained, so that lateral spacing design rules do not have to be increased. A thicker second epitaxial layer can thus be used, resulting in increased operating voltage.

摘要翻译： 描述了制造具有增加的工作电压的半导体器件的方法。 将第二导电类型的掺杂剂注入到第一导电类型的第一外延层的区域中以形成掩埋层。 然后将较小剂量的第二导电类型的较快扩散掺杂剂注入掩埋层区域。 第一导电类型的第二外延层形成在第一外延层上。 第二外延层的覆盖第一外延层的掺杂区域的区域被注入第二导电类型的掺杂剂并且扩散以形成掺杂阱。 较快扩散的掺杂​​剂向上扩散以与掺杂阱从表面向下扩散进行良好的电接触。 可以包含更快扩散的掺杂​​剂的横向扩散，使得横向间隔设计规则不必增加。 因此可以使用较厚的第二外延层，导致增加的工作电压。

公开(公告)号：US4637126A

公开(公告)日：1987-01-20

申请号：US771066

申请日：1985-08-30

申请人： Alexander W. Lightstone

发明人： Alexander W. Lightstone

IPC分类号： H01L31/107 ,  H01L21/302

CPC分类号： H01L31/107 ,  Y10S148/013

摘要： An avalanche photodiode includes a region of second conductivity type extending a distance into a substrate and a region of first conductivity type extending a further distance into the substrate of first conductivity type with a P-N junction therebetween. The invention is a method for fabricating an avalanche photodiode having a specified breakdown voltage. The method includes the step of measuring the concentration of the first type conductivity modifiers and removing a portion of the surface of the substrate prior to forming the region of second conductivity type. This method provides control of the concentration of the first type conductivity modifiers at the P-N junction and thereby controls the breakdown voltage.

摘要翻译： 雪崩光电二极管包括延伸到衬底中的距离的第二导电类型的区域和将第二导电类型的区域延伸到具有第一导电类型的衬底中的第二导电类型的区域，其间具有P-N结。 本发明是制造具有指定击穿电压的雪崩光电二极管的方法。 该方法包括在形成第二导电类型的区域之前测量第一类型电导率改性剂的浓度并去除衬底表面的一部分的步骤。 该方法提供对P-N结处的第一类型电导率调节剂的浓度的控制，从而控制击穿电压。

公开(公告)号：US5330922A

公开(公告)日：1994-07-19

申请号：US411782

申请日：1989-09-25

申请人： John P. Erdeljac ,  Louis N. Hutter

发明人： John P. Erdeljac ,  Louis N. Hutter

IPC分类号： H01L21/8249 ,  H01L21/265

CPC分类号： H01L21/8249 ,  Y10S148/013 ,  Y10S257/917 ,  Y10S257/929

摘要： A method of manufacturing semiconductor devices with increased operating voltages is described. A dopant of a second conductivity type is implanted into a region of a first epitaxial layer of the first conductivity type to form a buried layer. A substantially smaller dosage of a faster-diffusing dopant of the second conductivity type is then implanted into the buried layer region. The second epitaxial layer of the first conductivity type is formed over the first epitaxial layer. A region of the second epitaxial layer overlying the doped region of the first epitaxial layer is implanted with a dopant of the second conductivity type and diffused to form a doped well. The faster-diffusing dopant diffuses upward to make good electrical contact with the doped well diffusing downward from the surface. The lateral diffusion of the faster-diffusing dopant can be contained, so that lateral spacing design rules do not have to be increased. A thicker second epitaxial layer can thus be used, resulting in increased operating voltage.

摘要翻译： 描述了制造具有增加的工作电压的半导体器件的方法。 将第二导电类型的掺杂剂注入到第一导电类型的第一外延层的区域中以形成掩埋层。 然后将较小剂量的第二导电类型的较快扩散掺杂剂注入掩埋层区域。 第一导电类型的第二外延层形成在第一外延层上。 第二外延层的覆盖第一外延层的掺杂区域的区域被注入第二导电类型的掺杂剂并且扩散以形成掺杂阱。 较快扩散的掺杂​​剂向上扩散以与掺杂阱从表面向下扩散进行良好的电接触。 可以包含更快扩散的掺杂​​剂的横向扩散，使得横向间隔设计规则不必增加。 因此可以使用较厚的第二外延层，导致增加的工作电压。

公开(公告)号：US5273927A

公开(公告)日：1993-12-28

申请号：US889602

申请日：1992-05-27

申请人： Alfred P. Gnadinger

发明人： Alfred P. Gnadinger

IPC分类号： H01L27/115 ,  H01L21/76

CPC分类号： H01L27/11502 ,  Y10S148/013

摘要： Problems arise when connecting the bottom plate of a ferroelectric capacitor to the source of its associated access transistor during the fabrication of an ultra large scale integrated memory circuit. The temperature and ambient of certain steps of the fabrication process adversely affects ohmic properties of the connection. To overcome these problems, an insulative layer is formed between the bottom plate of a ferroelectric capacitor and its associated transistor. The insulative layer separates the source from the bottom electrode, and subsequent high temperature swings during the remainder of the fabrication process do not produce any direct connection between the source and the bottom plate. After the memory circuits have been fabricated on the semiconductor wafer, a voltage is applied across the ferroelectric capacitor and the insulative layer, preferably during a wafer probe. The magnitude of the applied voltage is selected to breakdown the insulative layer, but does not damage the ferroelectric layer. As a result, a good ohmic contact is produced between the bottom plate and the source of its associated transistor.

摘要翻译： 在制造超大规模集成存储器电路期间将铁电电容器的底板连接到其相关存取晶体管的源极时出现问题。 制造过程的某些步骤的温度和环境不利地影响连接的欧姆特性。 为了克服这些问题，在铁电电容器的底板与其相关联的晶体管之间形成绝缘层。 绝缘层将源极与底部电极分开，并且在制造过程的其余部分期间的随后的高温摆动不会在源极和底部板之间产生任何直接的连接。 在半导体晶片上制造存储器电路之后，优选在晶圆探针期间在铁电电容器和绝缘层之间施加电压。 选择施加电压的大小来击穿绝缘层，但不会损坏铁电层。 结果，在底板和其相关晶体管的源极之间产生良好的欧姆接触。

公开(公告)号：US5248623A

公开(公告)日：1993-09-28

申请号：US772472

申请日：1991-10-07

申请人： Hiroshi Muto ,  Masami Yamaoka

发明人： Hiroshi Muto ,  Masami Yamaoka

IPC分类号： H01L27/06 ,  H01L29/861

CPC分类号： H01L27/0688 ,  H01L29/861 ,  Y10S148/013

摘要： A diode which includes a first region formed in a polycrystalline silicon layer formed on a substrate. The diode has a predetermined width W and is one of an intrinsic region and a region including impurities at a low concentration therein, a second region and a third region including P-type impurities and N-type impurities therein respectively and both being oppositely arranged from each other with the first region therebetween in the polycrystalline silicon layer. Electrodes are electrically connected to the second region and the third region respectively, and further the film characteristic of the polycrystalline silicon layer and the predetermined width W thereof are determined in such a manner as to fulfill the following equation:W.sub.D .ltoreq.W.ltoreq.LL represents a carrier diffusion length and W.sub.D represents a width of the depletion layer created in the polycrystalline silicon layer when the voltage corresponding to the withstand voltage required by the polycrystalline diode as mentioned above, is applied thereto.

摘要翻译： 一种二极管，其包括形成在形成于基板上的多晶硅层中的第一区域。 二极管具有预定的宽度W，并且是本征区域和包括其中低浓度的杂质的区域中的一个，第二区域和分别包括P型杂质和N型杂质的第三区域，并且两者分别从 在多晶硅层中彼此具有第一区域。 电极分别电连接到第二区域和第三区域，并且进一步确定多晶硅层的膜特性和其预定宽度W，以便满足以下等式：WD

公开(公告)号：US6008512A

公开(公告)日：1999-12-28

申请号：US53243

申请日：1993-04-28

申请人： James D. Beasom

发明人： James D. Beasom

IPC分类号： H01L23/31 ,  H01L23/522 ,  H01L29/06 ,  H01L29/40 ,  H01L21/90

CPC分类号： H01L29/408 ,  H01L23/3192 ,  H01L23/5222 ,  H01L2924/0002 ,  Y10S148/013

摘要： In a semiconductor island structure with passive side isolation, a method and structure for reducing corner breakdown where a device conductor crosses the edge of the island. The decrease in the field strength at the island edge between the conductor and the adjacent conducting region may be achieved by increasing the depth of the insulator beneath the conductor where it crosses the island edge without the necessity for increasing the thickness of the layer of insulation applied directly to the surface of the island by the use of a second or higher level interconnect, e.g., the conventional deposition of one or more additional layers of insulation over the device terminal to increase the spacing between the conductor and the surface of the island. In this way the process by which the device is constructed may remain unchanged. The decrease in the field strength at the island edge may alternatively or in addition be achieved by increasing the thickness of the insulator providing lateral isolation without increasing the thickness of the substrate isolation by the use of lateral trench isolation formed independently of the substrate isolation.

摘要翻译： 在具有无源侧隔离的半导体岛结构中，用于减少器件导体跨越岛边缘的拐角击穿的方法和结构。 导体和相邻导电区域之间的岛边缘处的场强的减小可以通过增加导体下方的绝缘体的深度而越过岛边缘而实现，而不需要增加施加的绝缘层的厚度 通过使用第二或更高级别的互连（例如，在器件端子上常规沉积一个或多个额外的绝缘层）以增加导体和岛的表面之间的间隔直接到岛的表面。 以这种方式，构造装置的过程可以保持不变。 另外还可以通过增加提供横向隔离的绝缘体的厚度来实现岛边缘处的场强的降低，而不需要通过使用独立于衬底隔离而形成的侧向沟槽隔离来增加衬底隔离的厚度。

公开(公告)号：US5434095A

公开(公告)日：1995-07-18

申请号：US30797

申请日：1993-03-12

申请人： Theodore G. Hollinger

发明人： Theodore G. Hollinger

IPC分类号： H01L23/485 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L21/265

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L24/48 ,  H01L29/0847 ,  H01L29/42368 ,  H01L29/7802 ,  H01L2224/04042 ,  H01L2224/05001 ,  H01L2224/05082 ,  H01L2224/05624 ,  H01L2224/4847 ,  H01L2224/85424 ,  H01L29/1095 ,  H01L29/41766 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/13091 ,  Y10S148/013 ,  Y10S148/126 ,  Y10S148/151

摘要： A field-effect, power-MOS transistor wherein a region under the gate contact pad is specially doped with a dopant that is electrically compatible with that in the transistor's channel to obviate problems of electrical breakdown in that region.

摘要翻译： 场效应功率MOS晶体管，其中栅极接触焊盘下面的区域被特别地掺杂有与晶体管的沟道中的掺杂物电学相容的掺杂剂，以消除该区域中电击穿的问题。

公开(公告)号：US5399507A

公开(公告)日：1995-03-21

申请号：US265860

申请日：1994-06-27

申请人： Shih-Wei Sun

发明人： Shih-Wei Sun

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/76 ,  H01L21/822 ,  H01L21/84 ,  H01L27/08 ,  H01L27/12 ,  H01L29/786 ,  H01L21/265

CPC分类号： H01L21/84 ,  Y10S148/013

摘要： A mixed thin-film and bulk semiconductor substrate (10, 30) for integrated circuit applications is made with two different processes. In the first process, a standard wafer (11) is masked around its periphery (14). The internal unmasked portion (16) is implanted with an insulating species to form a buried dielectric layer (18), thus forming a mixed thin-film and bulk semiconductor substrate. Alternatively, a thin-film wafer may be masked on an internal portion (36) and then etched to expose a portion (40) of the underlying bulk substrate (11') around the periphery of the wafer. An epitaxial layer (50) is then grown to build up the exposed bulk portion to form the mixed substrate. An isolation region (24, 52, 46, 54) is formed at a boundary between the thin-film portion and the bulk portion. Devices (27, 28, 28') having different voltage requirements may then be formed overlying appropriate portions of the mixed substrate.

摘要翻译： 用于集成电路应用的混合薄膜和体半导体衬底（10,30）由两种不同的工艺制成。 在第一工艺中，标准晶片（11）围绕其周边（14）被掩蔽。 内部未屏蔽部分（16）注入绝缘材料以形成掩埋介电层（18），从而形成混合的薄膜和体半导体衬底。 或者，薄膜晶片可以被掩蔽在内部部分（36）上，然后被蚀刻以暴露围绕晶片周边的下面的块状基板（11'）的部分（40）。 然后生长外延层（50）以构成暴露的本体部分以形成混合的衬底。 在薄膜部分和本体部分之间的边界处形成隔离区域（24,52,46,54）。 然后可以形成具有不同电压要求的装置（27,28,28'），覆盖混合基板的适当部分。