公开(公告)号：US07852063B2

公开(公告)日：2010-12-14

申请号：US12133297

申请日：2008-06-04

申请人： Bun Kobayashi ,  Liyang Zhang ,  Mau-Chung Frank Chang ,  Pei-Ming Daniel Chow

发明人： Bun Kobayashi ,  Liyang Zhang ,  Mau-Chung Frank Chang ,  Pei-Ming Daniel Chow

IPC分类号： G01R5/22

CPC分类号： G01R21/12 ,  H03G3/3042 ,  H03G2201/708

摘要： An amplifier circuit comprises a detection power input circuit for receiving an RF signal, and a bias circuit that includes an output for generating a bias signal in response to a reference control voltage. The power detector further comprises a detection circuit for generating a power control voltage having a voltage characteristic that offsets temperature characteristics of the received RF signal. The amplifier circuit further comprises a power amplifier coupled to the bias circuit. The power amplifier includes a driver stage providing the RF signal. The detection circuit compensates temperature variation of the inputted detection voltage of the received RF signal.

摘要翻译： 放大器电路包括用于接收RF信号的检测功率输入电路和包括用于响应于参考控制电压产生偏置信号的输出的偏置电路。 功率检测器还包括用于产生具有抵消接收的RF信号的温度特性的电压特性的功率控制电压的检测电路。 放大器电路还包括耦合到偏置电路的功率放大器。 功率放大器包括提供RF信号的驱动级。 检测电路补偿接收到的RF信号的输入检测电压的温度变化。

公开(公告)号：US20100312926A1

公开(公告)日：2010-12-09

申请号：US12477799

申请日：2009-06-03

申请人： Siamak Arya ,  Fong-Long Lin ,  Thao Thach Tran

发明人： Siamak Arya ,  Fong-Long Lin ,  Thao Thach Tran

IPC分类号： G06F3/00 ,  H04B7/005

CPC分类号： H04M1/72527 ,  H04M1/2535

摘要： A USB switching device can selectively connect between a removable card and a mobile wireless communication device and a computer. The removable card has a first port; the mobile wireless communicating device has a second port while the computer has a third port. The switching device comprises a first full duplex switch having an input and a first output and a second output, and a select port for switching the connection of the input to the first output and the connection of the input to the second output. The switching device further comprises a second full duplex switch having an input and a first output and a second output, and a select port for switching the connection of the input to the first output and the connection of the input to the second output. The switching device further comprises a third full duplex switch having an input and a first output and a second output, and a select port for switching the connection of the input to the first output and the connection of the input to the second output. The input of the first switch is connected to the first port. The input of the second switch is connected to the second port. The input of the third switch is connected to the third port. The first output of the first switch is connected to the second output of the second switch. The second output of the first switch is connected to the first output of the third switch. Finally, the first output of the second switch is connected to the second output of the third switch.

摘要翻译： USB切换设备可以选择性地连接可移动卡与移动无线通信设备和计算机之间。 可拆卸卡具有第一端口; 移动无线通信设备具有第二端口，而计算机具有第三端口。 开关装置包括具有输入和第一输出和第二输出的第一全双工开关，以及用于将输入连接到第一输出和将输入连接到第二输出的选择端口。 开关装置还包括具有输入和第一输出和第二输出的第二全双工开关，以及用于将输入连接到第一输出和将输入连接到第二输出的选择端口。 开关装置还包括具有输入和第一输出和第二输出的第三全双工开关，以及用于将输入连接到第一输出和将输入连接到第二输出的选择端口。 第一开关的输入连接到第一端口。 第二开关的输入连接到第二端口。 第三开关的输入连接到第三端口。 第一开关的第一输出连接到第二开关的第二输出端。 第一开关的第二输出端连接到第三开关的第一输出端。 最后，第二开关的第一输出连接到第三开关的第二输出端。

公开(公告)号：US07848140B2

公开(公告)日：2010-12-07

申请号：US12507783

申请日：2009-07-22

申请人： Hieu Van Tran ,  Hung Quoc Nguyen ,  Anh Ly ,  Sheng-Hsiung Hsueh ,  Sang Thanh Nguyen ,  Loc B. Hoang ,  Steve Choi ,  Thuan T. Vu

发明人： Hieu Van Tran ,  Hung Quoc Nguyen ,  Anh Ly ,  Sheng-Hsiung Hsueh ,  Sang Thanh Nguyen ,  Loc B. Hoang ,  Steve Choi ,  Thuan T. Vu

IPC分类号： G11C16/04

CPC分类号： G11C8/10 ,  G11C16/0433 ,  G11C16/08 ,  G11C29/832

摘要： A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.

摘要翻译： 存储器系统包括布置在扇区中的存储器单元。 对应于扇区的解码器禁止具有缺陷顶门的存储单元。 解码器可以包括用于禁用的低电压或高电压锁存器。 包括顶栅处理算法。 存储器系统可以包括动态顶栅耦合。 包括具有顶栅处理的编程算法和波形。

公开(公告)号：US07829404B2

公开(公告)日：2010-11-09

申请号：US11950345

申请日：2007-12-04

申请人： Pavel Klinger ,  Amitay Levi

发明人： Pavel Klinger ,  Amitay Levi

IPC分类号： H01L21/8238

CPC分类号： H01L27/11521 ,  G11C16/0433 ,  H01L27/115 ,  H01L29/42328 ,  H01L29/7885

摘要： A memory device, and method of making and operating the same, including a substrate of semiconductor material of a first conductivity type, first and second spaced apart regions in the substrate of a second conductivity type with a channel region therebetween, an electrically conductive floating gate having a first portion disposed over and insulated from the channel region and a second portion disposed over and insulated from the first region and including a sharpened edge, an electrically conductive P/E gate having a first portion disposed over and insulated from the first region and a second portion extending up and over the floating gate second portion and insulated therefrom by a first layer of insulation material, and an electrically conductive select gate having a first portion disposed laterally adjacent to the floating gate and disposed over and insulated from the channel region.

摘要翻译： 存储器件及其制造和操作方法，包括第一导电类型的半导体材料的衬底，第二导电类型的衬底中的第一和第二间隔开的区域，其间具有沟道区，导电浮置栅极 具有设置在所述沟道区域上方并与所述沟道区域绝缘的第一部分和设置在所述第一区域上并与所述第一区域绝缘的第二部分，并且包括锐化边缘;导电P / E门，其具有设置在所述第一区域上方并与所述第一区域绝缘的第一部分， 第二部分，其在浮动栅极第二部分上方和上方延伸并且通过第一绝缘材料层与其绝缘;以及导电选择栅极，其具有横向邻近所述浮动栅极设置并设置在所述沟道区域上并与所述沟道区域绝缘的第一部分。

公开(公告)号：US20100254207A1

公开(公告)日：2010-10-07

申请号：US12725370

申请日：2010-03-16

申请人： Xian Liu ,  Michael James Heinz ,  Eugene Jinglun Tam ,  Michael K. Doan ,  Alexander Kotov ,  Tho Ngoc Dang ,  Jack Edward Frayer ,  Jung Hee Yun ,  Thuan T. Vu

发明人： Xian Liu ,  Michael James Heinz ,  Eugene Jinglun Tam ,  Michael K. Doan ,  Alexander Kotov ,  Tho Ngoc Dang ,  Jack Edward Frayer ,  Jung Hee Yun ,  Thuan T. Vu

IPC分类号： G11C7/00

CPC分类号： G11C7/00 ,  G11C7/14 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/28 ,  G11C2211/5634

摘要： A non-volatile memory device has an array of non-volatile memory cells, a first plurality of non-volatile memory reference cells, with each reference cell capable of being programmed to a reference level different from the other reference cells; and a second plurality of comparators. Each of the comparators is connectable to one of the first plurality of non-volatile memory reference cells and to one of a third plurality of memory cells from among the array of non-volatile memory cells.

摘要翻译： 非易失性存储器件具有非易失性存储器单元的阵列，第一多个非易失性存储器参考单元，每个参考单元能够被编程到与其它参考单元不同的参考电平; 和第二多个比较器。 每个比较器可从第一组非易失性存储器参考单元中的一个连接到非易失性存储器单元阵列中的第三多个存储器单元中的一个。

公开(公告)号：US07790518B2

公开(公告)日：2010-09-07

申请号：US12027916

申请日：2008-02-07

申请人： Bomy Chen ,  Ya-Fen Lin ,  Zhitang Song ,  Songlin Feng

发明人： Bomy Chen ,  Ya-Fen Lin ,  Zhitang Song ,  Songlin Feng

IPC分类号： H01L21/82

CPC分类号： H01L28/20 ,  H01C17/267 ,  H01L22/22

摘要： A method of trimming down the volume of a semiconductor resistor element using electrical resistance feedback. After forming conductive material disposed between a pair of electrodes, a voltage is applied to the electrodes to produce an electrical current through the conductive material sufficient to heat and melt away a portion of the conductive material. By reducing the volume of the conductive material, its resistance is increased. The application of the voltage is ceased once the desired dimensions (and thus resistivity) of the conductive material is reached. The resulting semiconductor resistor element could have a fixed resistance, or could have a variable resistance (by using phase change memory material).

摘要翻译： 使用电阻反馈来减少半导体电阻元件的体积的方法。 在形成设置在一对电极之间的导电材料之后，向电极施加电压以产生通过导电材料的电流，足以加热和熔化掉导电材料的一部分。 通过减小导电材料的体积，其电阻增加。 一旦达到导电材料的所需尺寸（因此电阻率），电压的施加就会停止。 所得到的半导体电阻元件可以具有固定电阻，或者可以具有可变电阻（通过使用相变存储器材料）。

公开(公告)号：US07737765B2

公开(公告)日：2010-06-15

申请号：US11080067

申请日：2005-03-14

申请人： Hieu Van Tran ,  Sang Thanh Nguyen ,  Anh Ly ,  Hung Q. Nguyen ,  Wingfu Aaron Lau ,  Nasrin Jaffari ,  Thuan Trong Vu ,  Vishal Sarin ,  Loc B. Hoang

发明人： Hieu Van Tran ,  Sang Thanh Nguyen ,  Anh Ly ,  Hung Q. Nguyen ,  Wingfu Aaron Lau ,  Nasrin Jaffari ,  Thuan Trong Vu ,  Vishal Sarin ,  Loc B. Hoang

IPC分类号： G05F1/10 ,  G05F3/02

CPC分类号： H02M3/07 ,  H02M1/36 ,  H02M1/44

摘要： A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping.

摘要翻译： 数字多电平存储器系统包括电荷泵和用于产生用于各种存储器操作的调节高电压的电压调节器。 电荷泵可以包括多个升压电路，以在快速启动期间升高电荷泵的输出。 之后，升压电路被禁止，使电荷泵产生高电压而不加速。 升压电路可以被连续地使能以升高电压。 升压电路可以是无负载的。 电压调节器可以在开环中工作，并且可以包括电阻分压器作为用于调节来自电荷泵的高电压的参考电压。 电荷泵可以包括扩频泵时钟，以减少用于电容器或电感器片上电荷泵浦的电磁推理。

公开(公告)号：US07718488B2

公开(公告)日：2010-05-18

申请号：US11380595

申请日：2006-04-27

申请人： Chiou-Feng Chen ,  Prateep Tuntasood ,  Der-Tsyr Fan

发明人： Chiou-Feng Chen ,  Prateep Tuntasood ,  Der-Tsyr Fan

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  G11C16/0425 ,  H01L27/115

摘要： Self-aligned split-gate flash memory cell array and process of fabrication in which erase and select gates are positioned on opposite sides of stacked floating and control gates, with source regions in the substrate beneath the erase gates, bit line diffusions which are partially overlapped by select gates at the ends of the rows of the cells. The floating and control gates are self-aligned with each other, and the erase and select gates are split from but self-aligned with the stacked gates. With the floating gates surrounded by the other gates and the source regions, high voltage coupling for both programming and erase operations is significantly enhanced. The memory cells are substantially smaller than prior art cells, and the array is biased so that all of the memory cells in it can be erased simultaneously, while programming is bit selectable.

摘要翻译： 自对准分离栅闪存单元阵列和制造工艺，其中擦除和选择栅极位于堆叠的浮置和控制栅极的相对侧上，源极区在擦除栅极下方的衬底中，位线扩散部分重叠 通过在单元格行的末端的选择门。 浮置和控制栅极彼此自对准，并且擦除和选择栅极与堆叠栅极分离，但是自对准。 由于其他栅极和源极区域所围绕的浮动栅极，编程和擦除操作的高电压耦合显着增强。 存储器单元比现有技术的单元小得多，并且阵列被偏置，使得其中的所有存储单元可以被同时擦除，而编程是位可选择的。

公开(公告)号：US20100091567A1

公开(公告)日：2010-04-15

申请号：US12637365

申请日：2009-12-14

申请人： Hieu Van Tran ,  Anh Ly ,  Sang Thanh Nguyen ,  Vishal Sarin ,  Hung Q. Nguyen ,  William John Saiki ,  Loc B. Hoang

发明人： Hieu Van Tran ,  Anh Ly ,  Sang Thanh Nguyen ,  Vishal Sarin ,  Hung Q. Nguyen ,  William John Saiki ,  Loc B. Hoang

IPC分类号： G11C16/04 ,  G11C29/00 ,  H03L5/00 ,  G01R19/00

CPC分类号： G11C11/5621 ,  G11C16/04 ,  G11C29/50 ,  G11C29/50004

摘要： A test device and method may be used to detect voltage, current or signals of a digital multilevel memory cell system or to test operation or performance by applying inputted voltages, currents or signals to the memory cell system.

摘要翻译： 可以使用测试装置和方法来检测数字多电平存储器单元系统的电压，电流或信号，或者通过将输入的电压，电流或信号施加到存储器单元系统来测试操作或性能。

公开(公告)号：US20100054043A1

公开(公告)日：2010-03-04

申请号：US12618632

申请日：2009-11-13

申请人： Xian Liu ,  Amitay Levi ,  Alexander Kotov ,  Yuri Tkachev ,  Viktor Markov ,  James Yingbo Jia ,  Chien-Sheng Su ,  Yaw Wen Hu

发明人： Xian Liu ,  Amitay Levi ,  Alexander Kotov ,  Yuri Tkachev ,  Viktor Markov ,  James Yingbo Jia ,  Chien-Sheng Su ,  Yaw Wen Hu

IPC分类号： G11C16/04 ,  H01L21/336 ,  G11C11/34 ,  H01L29/788

CPC分类号： H01L21/28273 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7883

摘要： An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in the substrate. The cell has a select gate above a portion of the channel region, a floating gate over another portion of the channel region, a control gate above the floating gate and an erase gate adjacent to the floating gate. The erase gate has an overhang extending over the floating gate. The ratio of the dimension of the overhang to the dimension of the vertical separation between the floating gate and the erase gate is between approximately 1.0 and 2.5, which improves erase efficiency.

摘要翻译： 改进的分裂门非易失性存储单元是在具有第二导电类型的第一区域和第二导电类型的第二区域的第一导电类型的基本单晶衬底中形成的，第一区域在第一区域之间 和底物中的第二区域。 单元在通道区域的一部分上方具有选择栅极，在沟道区域的另一部分上方的浮动栅极，浮置栅极上方的控制栅极和与浮动栅极相邻的擦除栅极。 擦除栅极具有在浮动栅极上延伸的突出端。 悬垂尺寸与浮动栅极和擦除栅极之间的垂直间隔的尺寸之比在1.0和2.5之间，这提高了擦除效率。