公开(公告)号：US12045150B2

公开(公告)日：2024-07-23

申请号：US17595454

申请日：2020-10-15

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Heng-Chia Chang ,  Chuanqi Shi ,  Li Ding

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/22 ,  G06F11/27

CPC classification number: G06F11/27 ,  G06F11/0793 ,  G06F11/2268

Abstract: Embodiments of the present disclosure provide a memory test method and a device thereof, an electronic device, and a computer-readable storage medium, which relate to the field of semiconductor device testing technologies. The method is executed by a built-in self-test circuit and includes: acquiring defect information of a first memory by testing the first memory; acquiring repair information of the first memory based on the defect information of the first memory; and storing the repair information of the first memory in a second memory.

公开(公告)号：US12041764B2

公开(公告)日：2024-07-16

申请号：US17449502

申请日：2021-09-30

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Gongyi Wu ,  Nan Deng ,  Yuchen Wang

IPC: H10B12/00

CPC classification number: H10B12/053 ,  H10B12/34

Abstract: A method for manufacturing a buried word line transistor can include the following operations. A semiconductor substrate having an active region is provided. A first trench is formed in the active region. A first insulation layer is formed on a side wall of the first trench. A bottom portion of the first trench is etched to form a second trench. A gate oxide layer is formed on a side wall of the first insulation layer and a bottom portion and a side wall of the second trench. A barrier layer is formed at a bottom portion and portion of a side wall of the gate oxide layer. A metal filler layer is formed on an inner side of the barrier layer. The first insulation layer is removed to form a side trench. A second insulation layer is formed at a top end of the side trench. A sealed air spacer layer is formed.

公开(公告)号：US12040296B2

公开(公告)日：2024-07-16

申请号：US17826222

申请日：2022-05-27

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Luguang Wang

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/81 ,  H01L2224/1308 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2224/13181 ,  H01L2224/81815 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/04941 ,  H01L2924/04953

Abstract: A semiconductor structure and a method for same are provided. The semiconductor structure includes: a first base having a first face, a second base having a second face, and a welding structure. The first base has an electrical connection column protruding from the first face. A first groove is provided at top of the electrical connection column. A conductive column is provided in the second base, and the second base also has a second groove. A top face and at least portion of a side face of the conductive column are exposed by the second groove. The electrical connection column is partially located in the second groove, and the conductive column is partially located in the first groove. At least portion of the welding structure is filled in the second groove, and at least further portion of the welding structure is filled between the conductive column and first groove.

公开(公告)号：US12033999B2

公开(公告)日：2024-07-09

申请号：US17472057

申请日：2021-09-10

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Qian Xu

IPC: H01L27/02

CPC classification number: H01L27/0262

Abstract: Provided is an electrostatic discharge protection device, including: a darlington structure formed in a substrate, and a diode string formed in the substrate and including a plurality of diodes connected in series. A first end of the darlington structure is connected to a first voltage, and a second end of the darlington structure is connected to a second voltage. An anode of the diode string is connected to a third end of the darlington structure. A cathode of the diode string is connected to the second voltage.

公开(公告)号：US12033933B2

公开(公告)日：2024-07-09

申请号：US17432191

申请日：2021-03-10

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Kaimin Lv

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/4846 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/13553 ,  H01L2224/13611 ,  H01L2224/16225 ,  H01L2224/81815 ,  H01L2924/1436 ,  H01L2924/182 ,  H01L2924/37001

Abstract: The present disclosure relates to the technical field of semiconductor packaging, and discloses a semiconductor structure and a method for forming the same. The method includes: providing a chip, the chip having interconnect structures on its surface, the top of the interconnect structures having an exposed fusible portion; providing a substrate, the substrate having conductive structures on its surface; patterning the conductive structures so that edges of the conductive structures have protrusions; combining the chip with the substrate.

公开(公告)号：US12033920B2

公开(公告)日：2024-07-09

申请号：US17511844

申请日：2021-10-27

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Pingheng Wu

IPC: H01L23/48 ,  H01L21/768 ,  H01L25/065

CPC classification number: H01L23/481 ,  H01L21/76877 ,  H01L21/76898 ,  H01L25/0657

Abstract: The present application relates to the field of semiconductor technologies, and discloses a semiconductor structure and a formation method thereof. The method includes: providing a semiconductor substrate, the semiconductor substrate including a TSV; forming a dielectric layer on a surface of the semiconductor substrate, the dielectric layer being provided with an embedded metal landing pad; and etching the dielectric layer to form a communication hole for communicating the TSV with the metal landing pad.

公开(公告)号：US12033911B2

公开(公告)日：2024-07-09

申请号：US17487869

申请日：2021-09-28

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Jie Liu ,  Lixia Zhang ,  Zhan Ying

IPC: H01L23/367

CPC classification number: H01L23/367

Abstract: Embodiments of the present application provide a semiconductor structure that comprises a semiconductor substrate having a first surface and a second surface opposite to the first surface, a solder pad located at the first surface, a heat transfer layer located at the first surface and being in contact with the solder pad, and a groove located in the semiconductor substrate and being connected to the heat transfer layer.

公开(公告)号：US12033689B2

公开(公告)日：2024-07-09

申请号：US17838596

申请日：2022-06-13

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Daoxun Wu ,  Weibing Shang

IPC: G11C11/4091

CPC classification number: G11C11/4091

Abstract: An amplification control method and circuit, a sensitive amplifier and a semiconductor memory are provided. The method includes that: a preset instruction is received, and an isolation power value and a control instruction signal are determined according to the preset instruction; an isolation control signal is generated according to the isolation power value and the control instruction signal; and an amplification circuit receives the isolation control signal and a target signal to be processed according to the preset instruction, and processes the signal to be processed and completes the preset instruction.

公开(公告)号：US12033685B2

公开(公告)日：2024-07-09

申请号：US17854273

申请日：2022-06-30

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Biao Cheng

IPC: G11C11/4076 ,  G11C29/02 ,  G11C7/04 ,  G11C7/22 ,  G11C29/50

CPC classification number: G11C11/4076 ,  G11C29/028 ,  G11C7/04 ,  G11C7/222 ,  G11C29/023 ,  G11C29/50012 ,  G11C2207/2254

Abstract: A method for adjusting margin, a circuit for adjusting margin, and a memory are provided. The method is applicable for a memory including a plurality of delay sub-circuits. The method includes: determining a voltage parameter and a temperature parameter, obtaining a target delay value by performing calculation on the voltage parameter and the temperature parameter through a preset time margin model; and adjusting a time margin of the memory by controlling working states of the plurality of delay sub-circuits according to the target delay value.

公开(公告)号：US12029026B2

公开(公告)日：2024-07-02

申请号：US17453046

申请日：2021-11-01

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Xiaoling Wang ,  Hai-Han Hung

IPC: H01L27/108 ,  H01L29/78 ,  H01L29/786 ,  H10B12/00

CPC classification number: H10B12/05 ,  H01L29/7853 ,  H01L29/78642 ,  H10B12/315 ,  H10B12/482

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure and a semiconductor structure, relating to the technical field of semiconductors. The method of manufacturing a semiconductor structure includes: providing a substrate; forming active pillars arranged in an array on the substrate, a projection shape of a longitudinal section of each of the active pillars includes a cross shape; forming a first oxide layer on the substrate, where a filling region is formed between adjacent active pillars in the same row; sequentially forming a word line and a dielectric layer in the filling region; exposing a top surface of each of the active pillars; forming a contact layer on the active pillars; and forming a capacitor structure on the contact layer.