公开(公告)号：US5013395A

公开(公告)日：1991-05-07

申请号：US91009

申请日：1987-08-28

Applicant: Lawrence R. Blumberg ,  Douglas D. Coolbaugh ,  John A. Kurowski ,  Eugene A. Stromecki

Inventor： Lawrence R. Blumberg ,  Douglas D. Coolbaugh ,  John A. Kurowski ,  Eugene A. Stromecki

IPC: C23F1/46 ,  H05K3/06

CPC classification number: C23F1/46

Abstract: A method of continuously regenerating a metal containing acid solution enhanced with a salt-free material. The metal dissolved in a bulk metal containing acid solution is continuously oxidized by introducing a gas into a packed reaction vessel. The packed reaction vessel is in operative relationship with the bulk acid solution for recirculating regenerated solution and for receiving spent solution. The gas is introduced substantially cocurrently with the spent acid solution.

公开(公告)号：US08872281B2

公开(公告)日：2014-10-28

申请号：US13570737

申请日：2012-08-09

Applicant: Douglas D. Coolbaugh ,  Jeffrey B. Johnson ,  Peter J. Lindgren ,  Xuefeng Lie ,  James S. Nakos ,  Bradley A. Omer ,  Robert M. Rassel ,  David C. Sheridan

Inventor： Douglas D. Coolbaugh ,  Jeffrey B. Johnson ,  Peter J. Lindgren ,  Xuefeng Lie ,  James S. Nakos ,  Bradley A. Omer ,  Robert M. Rassel ,  David C. Sheridan

IPC: H01L29/78 ,  H01L21/74 ,  H01L21/762

CPC classification number: H01L21/743 ,  H01L21/28518 ,  H01L21/76224 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/41 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A trench contact silicide is formed on an inner wall of a contact trench that reaches to a buried conductive layer in a semiconductor substrate to reduce parasitic resistance of a reachthrough structure. The trench contact silicide is formed at the bottom, on the sidewalls of the trench, and on a portion of the top surface of the semiconductor substrate. The trench is subsequently filled with a middle-of-line (MOL) dielectric. A contact via may be formed on the trench contact silicide. The trench contact silicide may be formed through a single silicidation reaction with a metal layer or through multiple silicidation reactions with multiple metal layers.

Abstract translation: 沟槽接触硅化物形成在接触沟槽的内壁上，该接触沟槽的内壁到达半导体衬底中的掩埋导电层，以减小通孔结构的寄生电阻。 沟槽接触硅化物形成在底部，沟槽的侧壁上以及在半导体衬底的顶表面的一部分上。 沟槽随后填充有中间线（MOL）电介质。 可以在沟槽接触硅化物上形成接触通孔。 沟槽接触硅化物可以通过与金属层的单一硅化反应或通过与多个金属层的多次硅化反应形成。

公开(公告)号：US20140239498A1

公开(公告)日：2014-08-28

申请号：US13570737

申请日：2012-08-09

Applicant: Douglas D. Coolbaugh ,  Jeffrey B. Johnson ,  Peter J. Lindgren ,  Xuefeng Liu ,  James S. Nakos ,  Bradley A. Orner ,  Robert M. Rassel ,  David C. Sheridan

Inventor： Douglas D. Coolbaugh ,  Jeffrey B. Johnson ,  Peter J. Lindgren ,  Xuefeng Liu ,  James S. Nakos ,  Bradley A. Orner ,  Robert M. Rassel ,  David C. Sheridan

IPC: H01L23/48 ,  H01L23/482

CPC classification number: H01L21/743 ,  H01L21/28518 ,  H01L21/76224 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/41 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A trench contact silicide is formed on an inner wall of a contact trench that reaches to a buried conductive layer in a semiconductor substrate to reduce parasitic resistance of a reachthrough structure. The trench contact silicide is formed at the bottom, on the sidewalls of the trench, and on a portion of the top surface of the semiconductor substrate. The trench is subsequently filled with a middle-of-line (MOL) dielectric. A contact via may be formed on the trench contact silicide. The trench contact silicide may be formed through a single silicidation reaction with a metal layer or through multiple silicidation reactions with multiple metal layers.

Abstract translation: 沟槽接触硅化物形成在接触沟槽的内壁上，该接触沟槽的内壁到达半导体衬底中的掩埋导电层，以减小通孔结构的寄生电阻。 沟槽接触硅化物形成在底部，沟槽的侧壁上以及在半导体衬底的顶表面的一部分上。 沟槽随后填充有中间线（MOL）电介质。 可以在沟槽接触硅化物上形成接触通孔。 沟槽接触硅化物可以通过与金属层的单一硅化反应或通过与多个金属层的多次硅化反应形成。

公开(公告)号：US08609505B2

公开(公告)日：2013-12-17

申请号：US13359032

申请日：2012-01-26

Applicant: Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Robert M. Rassel ,  Anthony K. Stamper

Inventor： Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Robert M. Rassel ,  Anthony K. Stamper

IPC: H01L27/06 ,  H01L27/07 ,  H01L21/20

CPC classification number: H01L27/0629 ,  H01L28/60

Abstract: A capacitor structure includes a semiconductor substrate; a first capacitor plate positioned on the semiconductor substrate, the first capacitor plate including a polysilicon structure having a surrounding spacer; a silicide layer formed in a first portion of an upper surface of the first capacitor plate; a capacitor dielectric layer formed over a second portion of the upper surface of the first capacitor plate and extending laterally beyond the spacer to contact the semiconductor substrate; a contact in an interlayer dielectric (ILD), the contact contacting the silicide layer and a first metal layer over the ILD; and a second capacitor plate over the capacitor dielectric layer, wherein a metal-insulator-metal (MIM) capacitor is formed by the first capacitor plate, the capacitor dielectric layer and the second capacitor plate and a metal-insulator-semiconductor (MIS) capacitor is formed by the second capacitor plate, the capacitor dielectric layer and the semiconductor substrate.

Abstract translation: 电容器结构包括半导体衬底; 位于所述半导体衬底上的第一电容器板，所述第一电容器板包括具有周围间隔物的多晶硅结构; 硅化物层，形成在所述第一电容器板的上表面的第一部分中; 电容器电介质层，形成在第一电容器板的上表面的第二部分上并且横向延伸超过间隔物以接触半导体衬底; 在层间电介质（ILD）中的接触，接触硅化物层的接触和ILD上的第一金属层; 以及在所述电容器电介质层上的第二电容器板，其中由所述第一电容器板，所述电容器介电层和所述第二电容器板以及金属 - 绝缘体 - 半导体（MIS）电容器形成金属 - 绝缘体 - 金属（MIM）电容器 由第二电容器板，电容器电介质层和半导体衬底形成。

公开(公告)号：US08378450B2

公开(公告)日：2013-02-19

申请号：US12548484

申请日：2009-08-27

Applicant: Roger A. Booth, Jr. ,  Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Zhong-Xiang He

Inventor： Roger A. Booth, Jr. ,  Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Zhong-Xiang He

IPC: H01L29/92 ,  H01L21/02

CPC classification number: H01L28/90 ,  H01L23/5223 ,  H01L28/86 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interdigitated structure may include at least one first metal line, at least one second metal line parallel to the at least one first metal line and separated from the at least one first metal line, and a third metal line contacting ends of the at least one first metal line and separated from the at least one second metal line. The at least one first metal line does not vertically contact any metal via and at least one second metal line may vertically contact at least one metal via. Multiple layers of interdigitated structure may be vertically stacked. Alternately, an interdigitated structure may include a plurality of first metal lines and a plurality of second metal lines, each metal line not vertically contacting any metal via. Multiple instances of interdigitated structure may be laterally replicated and adjoined, with or without rotation, and/or vertically stacked to form a capacitor.

Abstract translation: 叉指结构可以包括至少一个第一金属线，平行于至少一个第一金属线并与至少一个第一金属线分离的至少一个第二金属线，以及接触至少一个第一金属线的端部的第三金属线 第一金属线并且与所述至少一个第二金属线分离。 所述至少一个第一金属线不垂直接触任何金属通孔，并且至少一个第二金属线可垂直接触至少一个金属通孔。 多层交错结构可以垂直堆叠。 替代地，叉指结构可以包括多个第一金属线和多个第二金属线，每个金属线不垂直地接触任何金属通孔。 交错结构的多个实例可以横向复制和邻接，具有或不具有旋转和/或垂直堆叠以形成电容器。

公开(公告)号：US20120214280A1

公开(公告)日：2012-08-23

申请号：US13460871

申请日：2012-05-01

Applicant: Douglas D. COOLBAUGH ,  Ebenezer E. ESHUN ,  Terence B. HOOK ,  Robert M. RASSEL ,  Edmund J. SPROGIS ,  Anthony K. STAMPER ,  William J. MURPHY

Inventor： Douglas D. COOLBAUGH ,  Ebenezer E. ESHUN ,  Terence B. HOOK ,  Robert M. RASSEL ,  Edmund J. SPROGIS ,  Anthony K. STAMPER ,  William J. MURPHY

IPC: H01L21/50

CPC classification number: H01C7/1013 ,  H01C1/084 ,  H01L2924/0002 ,  Y10T29/49083 ,  Y10T29/49085 ,  Y10T29/49099 ,  Y10T29/49144 ,  Y10T29/49147 ,  H01L2924/00

Abstract: A resistor with heat sink is provided. The heat sink includes a conductive path having metal or other thermal conductor having a high thermal conductivity. To avoid shorting the electrical resistor to ground with the thermal conductor, a thin layer of high thermal conductivity electrical insulator is interposed between the thermal conductor and the body of the resistor. Accordingly, a resistor can carry large amounts of current because the high conductivity thermal conductor will conduct heat away from the resistor to a heat sink. Various configurations of thermal conductors and heat sinks are provided offering good thermal conductive properties in addition to reduced parasitic capacitances and other parasitic electrical effects, which would reduce the high frequency response of the electrical resistor.

Abstract translation: 提供带散热片的电阻。 散热器包括具有导热性高的金属或其它热导体的导电路径。 为了避免使用热导体将电阻器短路接地，在热导体和电阻体之间插入有一层薄导电电绝缘体。 因此，电阻器可承载大量的电流，因为高导电性热导体将热量从电阻器传导到散热器。 除了降低寄生电容和其他寄生电效应之外，提供各种配置的导热体和散热片，提供良好的导热性能，这将降低电阻器的高频响应。

公开(公告)号：US08236663B2

公开(公告)日：2012-08-07

申请号：US12564482

申请日：2009-09-22

Applicant: Douglas D. Coolbaugh ,  Keith E. Downes ,  Peter J Lindgren ,  Anthony K. Stamper

Inventor： Douglas D. Coolbaugh ,  Keith E. Downes ,  Peter J Lindgren ,  Anthony K. Stamper

IPC: H01L21/20

CPC classification number: H01L23/481 ,  H01L21/76808 ,  H01L21/76813 ,  H01L21/76832 ,  H01L23/5223 ,  H01L28/60 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method and semiconductor device. In the method, at least one partial via is etched in a stacked structure and a border is formed about the at least one partial via. The method further includes performing thick wiring using selective etching while continuing via etching to at least one etch stop layer.

Abstract translation: 一种方法和半导体器件。 在该方法中，至少一个部分通孔被蚀刻成堆叠结构，围绕至少一个部分通孔形成边界。 该方法还包括使用选择性蚀刻执行厚布线，同时通过蚀刻继续至少一个蚀刻停止层。

公开(公告)号：US08227849B2

公开(公告)日：2012-07-24

申请号：US12706834

申请日：2010-02-17

Applicant: Ebenezer E Eshun ,  Ronald J Bolam ,  Douglas D Coolbaugh ,  Keith E Downes ,  Natalie B Feilchenfeld ,  Zhong-Xiang He

Inventor： Ebenezer E Eshun ,  Ronald J Bolam ,  Douglas D Coolbaugh ,  Keith E Downes ,  Natalie B Feilchenfeld ,  Zhong-Xiang He

IPC: H01L29/92

CPC classification number: H01L28/60

Abstract: The invention is directed to an improved capacitor that reduces edge defects and prevents yield failures. A first embodiment of the invention comprises a protective layer adjacent an interface of a conductive layer with the insulator, while the second embodiment of the invention comprises a protective layer on an insulator which is on a conductive layer.

Abstract translation: 本发明涉及一种改进的电容器，其减少边缘缺陷并防止产量失效。 本发明的第一实施例包括与导电层与绝缘体的界面相邻的保护层，而本发明的第二实施例包括位于导电层上的绝缘体上的保护层。

公开(公告)号：US20120184081A1

公开(公告)日：2012-07-19

申请号：US13432440

申请日：2012-03-28

Applicant: Anil K. CHINTHAKINDI ,  Douglas D. COOLBAUGH ,  Keith E. DOWNES ,  Ebenezer E. ESHUN ,  Zhong-Xiang HE ,  Robert M. RASSEL ,  Anthony K. STAMPER

Inventor： Anil K. CHINTHAKINDI ,  Douglas D. COOLBAUGH ,  Keith E. DOWNES ,  Ebenezer E. ESHUN ,  Zhong-Xiang HE ,  Robert M. RASSEL ,  Anthony K. STAMPER

IPC: H01L21/02

CPC classification number: H01L21/32139 ,  H01L21/32136 ,  H01L28/75

Abstract: A method of fabricating a MIM capacitor is provided. The method includes providing a substrate including a dielectric layer formed on a first conductive layer and a second conductive layer formed over the dielectric layer, and patterning a mask on the second conductive layer. Exposed portions of the second conductive layer are removed to form an upper plate of a MIM capacitor having edges substantially aligned with respective edges of the mask. The upper plate is undercut so that edges of the upper plate are located under the mask. Exposed portions of the dielectric layer and the first conductive layer are removed using the mask to form a capacitor dielectric layer and a lower plate of the MIM capacitor having edges substantially aligned with respective edges of the mask.

Abstract translation: 提供一种制造MIM电容器的方法。 该方法包括提供包括形成在第一导电层上的电介质层和形成在电介质层上的第二导电层的衬底，以及在第二导电层上构图掩模。 去除第二导电层的暴露部分以形成具有与掩模的相应边缘基本对齐的边缘的MIM电容器的上板。 上板被切下，使得上板的边缘位于掩模下方。 使用掩模去除电介质层和第一导电层的暴露部分，以形成MIM电容器的电容器电介质层和具有基本上与掩模的各个边缘对准的边缘的MIM电容器的下板。

公开(公告)号：US08207568B2

公开(公告)日：2012-06-26

申请号：US11162661

申请日：2005-09-19

Applicant: Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Keith E. Downes ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Robert M. Rassel ,  Anthony K. Stamper

Inventor： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Keith E. Downes ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Robert M. Rassel ,  Anthony K. Stamper

IPC: H01L29/92

CPC classification number: H01L21/32139 ,  H01L21/32136 ,  H01L28/75

Abstract: Method of fabricating a MIM capacitor and MIM capacitor. The method includes providing a substrate including a dielectric layer formed on a first conductive layer and a second conductive layer formed over the dielectric layer, and patterning a mask on the second conductive layer. Exposed portions of the second conductive layer are removed to form an upper plate of a MIM capacitor having edges substantially aligned with respective edges of the mask. The upper plate is undercut so that edges of the upper plate are located under the mask. Exposed portions of the dielectric layer and the first conductive layer are removed using the mask to form a capacitor dielectric layer and a lower plate of the MIM capacitor having edges substantially aligned with respective edges of the mask.

Abstract translation: 制造MIM电容器和MIM电容器的方法。 该方法包括提供包括形成在第一导电层上的电介质层和形成在电介质层上的第二导电层的衬底，以及在第二导电层上构图掩模。 去除第二导电层的暴露部分以形成具有与掩模的相应边缘基本对齐的边缘的MIM电容器的上板。 上板被切下，使得上板的边缘位于掩模下方。 使用掩模去除电介质层和第一导电层的暴露部分，以形成MIM电容器的电容器电介质层和具有基本上与掩模的各个边缘对准的边缘的MIM电容器的下板。