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    Process for single and multiple level metal-insulator-metal integration with a single mask
    7.
    发明授权
    Process for single and multiple level metal-insulator-metal integration with a single mask 有权
    单层和多层金属绝缘体金属与单一掩模集成的工艺

    公开(公告)号：US08435864B2

    公开(公告)日：2013-05-07

    申请号：US13432440

    申请日：2012-03-28

    申请人： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Keith E. Downes ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Robert M. Rassel ,  Anthony K. Stamper

    发明人： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Keith E. Downes ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Robert M. Rassel ,  Anthony K. Stamper

    IPC分类号： H01L21/28

    CPC分类号： H01L21/32139 ,  H01L21/32136 ,  H01L28/75

    摘要： A method of fabricating a MIM capacitor is provided. The method includes providing a substrate including a dielectric layer formed on a first conductive layer and a second conductive layer formed over the dielectric layer, and patterning a mask on the second conductive layer. Exposed portions of the second conductive layer are removed to form an upper plate of a MIM capacitor having edges substantially aligned with respective edges of the mask. The upper plate is undercut so that edges of the upper plate are located under the mask. Exposed portions of the dielectric layer and the first conductive layer are removed using the mask to form a capacitor dielectric layer and a lower plate of the MIM capacitor having edges substantially aligned with respective edges of the mask.

    摘要翻译： 提供一种制造MIM电容器的方法。 该方法包括提供包括形成在第一导电层上的电介质层和形成在电介质层上的第二导电层的衬底，以及在第二导电层上构图掩模。 去除第二导电层的暴露部分以形成具有与掩模的相应边缘基本对齐的边缘的MIM电容器的上板。 上板被切下，使得上板的边缘位于掩模下方。 使用掩模去除电介质层和第一导电层的暴露部分，以形成MIM电容器的电容器电介质层和具有基本上与掩模的各个边缘对准的边缘的MIM电容器的下板。

    Process for single and multiple level metal-insulator-metal integration with a single mask
    8.
    发明授权
    Process for single and multiple level metal-insulator-metal integration with a single mask 有权
    单层和多层金属绝缘体金属与单一掩模集成的工艺

    公开(公告)号：US08207568B2

    公开(公告)日：2012-06-26

    申请号：US11162661

    申请日：2005-09-19

    申请人： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Keith E. Downes ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Robert M. Rassel ,  Anthony K. Stamper

    发明人： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Keith E. Downes ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Robert M. Rassel ,  Anthony K. Stamper

    IPC分类号： H01L29/92

    CPC分类号： H01L21/32139 ,  H01L21/32136 ,  H01L28/75

    摘要： Method of fabricating a MIM capacitor and MIM capacitor. The method includes providing a substrate including a dielectric layer formed on a first conductive layer and a second conductive layer formed over the dielectric layer, and patterning a mask on the second conductive layer. Exposed portions of the second conductive layer are removed to form an upper plate of a MIM capacitor having edges substantially aligned with respective edges of the mask. The upper plate is undercut so that edges of the upper plate are located under the mask. Exposed portions of the dielectric layer and the first conductive layer are removed using the mask to form a capacitor dielectric layer and a lower plate of the MIM capacitor having edges substantially aligned with respective edges of the mask.

    摘要翻译： 制造MIM电容器和MIM电容器的方法。 该方法包括提供包括形成在第一导电层上的电介质层和形成在电介质层上的第二导电层的衬底，以及在第二导电层上构图掩模。 去除第二导电层的暴露部分以形成具有与掩模的相应边缘基本对齐的边缘的MIM电容器的上板。 上板被切下，使得上板的边缘位于掩模下方。 使用掩模去除电介质层和第一导电层的暴露部分，以形成MIM电容器的电容器电介质层和具有基本上与掩模的各个边缘对准的边缘的MIM电容器的下板。

    Metal seed layer deposition
    10.
    发明授权
    Metal seed layer deposition 有权
    金属种子层沉积

    公开(公告)号：US07879716B2

    公开(公告)日：2011-02-01

    申请号：US11687017

    申请日：2007-03-16

    申请人： Steven P. Barkyoumb ,  Jonathan D. Chapple-Sokol ,  Edward C. Cooney, III ,  Keith E. Downes ,  Thomas L. McDevitt ,  William J. Murphy

    发明人： Steven P. Barkyoumb ,  Jonathan D. Chapple-Sokol ,  Edward C. Cooney, III ,  Keith E. Downes ,  Thomas L. McDevitt ,  William J. Murphy

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76843 ,  H01L21/76856 ,  H01L21/76859 ,  H01L21/76861 ,  H01L21/76862 ,  H01L21/76871 ,  H01L21/76873

    摘要： A method and structure for reducing the corrosion of the copper seed layer during the fabrication process of a semiconductor structure. Before the structure (or the wafer containing the structure) exits the vacuum environment of the sputter tool, the structure is warmed up to a temperature above the water condensation temperature of the environment outside the sputter tool. As a result, water vapor would not condense on the structure when the structure exits the sputter tool, and therefore, corrosion of the seed layer by the water vapor is prevented. Alternatively, a protective layer resistant to water vapor can be formed on top of the seed layer before the structure exits the sputter tool environment. In yet another alternative embodiment, the seed layer can comprises a copper alloy (such as with aluminum) which grows a protective layer resistant to water vapor upon exposure to water vapor.

    摘要翻译： 一种用于在半导体结构的制造过程中减少铜籽晶层的腐蚀的方法和结构。 在结构（或包含结构的晶片）离开溅射工具的真空环境之前，将结构加热到高于溅射工具外部环境的水冷凝温度的温度。 结果，当结构离开溅射工具时，水蒸气不会在结构上冷凝，因此防止了水蒸气对种子层的腐蚀。 或者，在结构离开溅射工具环境之前，可以在籽晶层的顶部形成耐水蒸汽的保护层。 在另一替代实施例中，种子层可以包括铜合金（例如用铝），其在暴露于水蒸汽时生长出耐水蒸气的保护层。