公开(公告)号：US07886240B2

公开(公告)日：2011-02-08

申请号：US12021333

申请日：2008-01-29

Applicant: James W. Adkisson ,  Natalie B. Feilchenfeld ,  Jeffrey P. Gambino ,  Howard S. Landis ,  Benjamin T. Voegeli ,  Steven H. Voldman ,  Michael J. Zierak

Inventor： James W. Adkisson ,  Natalie B. Feilchenfeld ,  Jeffrey P. Gambino ,  Howard S. Landis ,  Benjamin T. Voegeli ,  Steven H. Voldman ,  Michael J. Zierak

IPC: G06F17/50 ,  G06F7/38 ,  H01L25/00 ,  H03K19/00

CPC classification number: G06F17/5081

Abstract: Modifying a layout of an integrated circuit (IC) based on a function of an interconnect therein and a related circuit and design structure are disclosed. In one embodiment, a method includes identifying a function of an interconnect in the layout from data of the layout embodied in a computer readable medium; and modifying the layout to form another layout that accommodates the function of the interconnect. A design structure embodied in a machine readable medium used in a design process, according to one embodiment, may include a circuit including a high voltage interconnect positioned in a dielectric layer, the high voltage interconnect positioned such that no fill is above or below the high voltage interconnect.

Abstract translation: 公开了基于互连功能的集成电路（IC）的布局以及相关的电路和设计结构。 在一个实施例中，一种方法包括根据体现在计算机可读介质中的布局的数据来识别布局中的互连的功能; 并修改布局以形成适应互连功能的另一布局。 根据一个实施例，体现在设计过程中使用的机器可读介质中的设计结构可以包括电路，该电路包括定位在电介质层中的高电压互连，所述高压互连被定位成使得没有填充物高于或低于高 电压互连。

公开(公告)号：US20090261426A1

公开(公告)日：2009-10-22

申请号：US12104643

申请日：2008-04-17

Applicant: Natalie B. Feilchenfeld ,  Jeffrey P. Gambino ,  Xuefeng Liu ,  Benjamin T. Voegeli ,  Steven H. Voldman ,  Michael J. Zierak

Inventor： Natalie B. Feilchenfeld ,  Jeffrey P. Gambino ,  Xuefeng Liu ,  Benjamin T. Voegeli ,  Steven H. Voldman ,  Michael J. Zierak

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L21/26586 ,  H01L21/26513 ,  H01L29/1045 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/7835

Abstract: A disposable structure displaced from an edge of a gate electrode and a drain region aligned to the disposable structure is formed. Thus, the drain region is self-aligned to the edge of the gate electrode. The disposable structure may be a disposable spacer, or alternately, the disposable structure may be formed simultaneously with, and comprise the same material as, a gate electrode. After formation of the drain regions, the disposable structure is removed. The self-alignment of the drain region to the edge of the gate electrode provides a substantially constant drift distance that is independent of any overlay variation of lithographic processes.

Abstract translation: 形成从栅电极的边缘排列的一次性结构和与一次性结构对准的漏区。 因此，漏极区域与栅电极的边缘自对准。 一次性结构可以是一次性间隔件，或者替代地，一次性结构可以与栅电极同时形成并且包括与栅电极相同的材料。 在形成漏极区域之后，一次性结构被去除。 漏极区域到栅电极的边缘的自对准提供了与光刻工艺的任何叠加变化无关的基本恒定的漂移距离。

公开(公告)号：US08946013B2

公开(公告)日：2015-02-03

申请号：US13364663

申请日：2012-02-02

Applicant: Natalie B. Feilchenfeld ,  Jeffrey P. Gambino ,  Xuefeng Liu ,  Benjamin T. Voegeli ,  Steven H. Voldman ,  Michael J. Zierak

Inventor： Natalie B. Feilchenfeld ,  Jeffrey P. Gambino ,  Xuefeng Liu ,  Benjamin T. Voegeli ,  Steven H. Voldman ,  Michael J. Zierak

IPC: H01L21/00 ,  H01L21/265 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L21/26586 ,  H01L21/26513 ,  H01L29/1045 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/7835

Abstract: A disposable structure displaced from an edge of a gate electrode and a drain region aligned to the disposable structure is formed. Thus, the drain region is self-aligned to the edge of the gate electrode. The disposable structure may be a disposable spacer, or alternately, the disposable structure may be formed simultaneously with, and comprise the same material as, a gate electrode. After formation of the drain regions, the disposable structure is removed. The self-alignment of the drain region to the edge of the gate electrode provides a substantially constant drift distance that is independent of any overlay variation of lithographic processes.

Abstract translation: 形成从栅电极的边缘排列的一次性结构和与一次性结构对准的漏区。 因此，漏极区域与栅电极的边缘自对准。 一次性结构可以是一次性间隔件，或者替代地，一次性结构可以与栅电极同时形成并且包括与栅电极相同的材料。 在形成漏极区域之后，一次性结构被去除。 漏极区域到栅电极的边缘的自对准提供了与光刻工艺的任何叠加变化无关的基本恒定的漂移距离。

公开(公告)号：US08492866B1

公开(公告)日：2013-07-23

申请号：US13345881

申请日：2012-01-09

Applicant: Frederick G. Anderson ,  Natalie B. Feilchenfeld ,  David L. Harmon ,  Richard A. Phelps ,  Yun Shi ,  Michael J. Zierak

Inventor： Frederick G. Anderson ,  Natalie B. Feilchenfeld ,  David L. Harmon ,  Richard A. Phelps ,  Yun Shi ,  Michael J. Zierak

IPC: H01L29/861 ,  H01L31/107 ,  H01L29/30 ,  H01L29/866 ,  H01L29/34 ,  H01L29/74 ,  H01L31/111 ,  H01L29/73 ,  H01L29/739 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109 ,  H01L29/00 ,  H01L29/864

CPC classification number: H01L29/866 ,  H01L21/76 ,  H01L21/76283 ,  H01L27/0255 ,  H01L29/66106

Abstract: Disclosed is a Zener diode having a scalable reverse-bias breakdown voltage (Vb) as a function of the position of a cathode contact region relative to the interface between adjacent cathode and anode well regions. Specifically, cathode and anode contact regions are positioned adjacent to corresponding cathode and anode well regions and are further separated by an isolation region. However, while the anode contact region is contained entirely within the anode well region, one end of the cathode contact region extends laterally into the anode well region. The length of this end can be predetermined in order to selectively adjust the Vb of the diode (e.g., increasing the length reduces Vb of the diode and vice versa). Also disclosed are an integrated circuit, incorporating multiple instances of the diode with different reverse-bias breakdown voltages, a method of forming the diode and a design structure for the diode.

Abstract translation: 公开了一种齐纳二极管，其具有作为阴极接触区域相对于相邻阴极和阳极阱区域之间的界面的位置的函数的可分级反向偏压击穿电压（Vb）。 具体地，阴极和阳极接触区域被定位成与相应的阴极和阳极阱区域相邻，并进一步被隔离区域分离。 然而，当阳极接触区域完全包含在阳极阱区域内时，阴极接触区域的一端横向延伸到阳极阱区域中。 为了选择性地调节二极管的Vb（例如，增加长度减小二极管的Vb，反之亦然），可以预定该端的长度。 还公开了一种集成电路，其结合具有不同反向偏压击穿电压的二极管的多个实例，形成二极管的方法和二极管的设计结构。

公开(公告)号：US08236662B2

公开(公告)日：2012-08-07

申请号：US12949108

申请日：2010-11-18

Applicant: Natalie B. Feilchenfeld ,  Bradley A. Orner ,  Benjamin T. Voegeli

Inventor： Natalie B. Feilchenfeld ,  Bradley A. Orner ,  Benjamin T. Voegeli

IPC: H01L21/8249

CPC classification number: H01L29/7302 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/1004 ,  H01L29/66287

Abstract: High performance bipolar transistors with raised extrinsic self-aligned base are integrated into a BiCMOS structure containing CMOS devices. By forming pad layers and raising the height of an intrinsic base layer relative to the source and drain of preexisting CMOS devices and by forming an extrinsic base through selective epitaxy, the effect of topographical variations is minimized during a lithographic patterning of the extrinsic base. Also, by not employing any chemical mechanical planarization process during the fabrication of the bipolar structures, complexity of process integration is reduced. Internal spacers or external spacers may be formed to isolate the base from the emitter. The pad layers, the intrinsic base layer, and the extrinsic base layer form a mesa structure with coincident outer sidewall surfaces.

Abstract translation: 具有凸起的外部自对准基极的高性能双极晶体管集成到包含CMOS器件的BiCMOS结构中。 通过形成焊盘层并相对于先前存在的CMOS器件的源极和漏极提高本征基极层的高度，并且通过选择性外延形成外部基极，在外部基极的光刻图案化期间，拓扑变化的影响被最小化。 而且，通过在双极结构的制造期间不采用任何化学机械平面化工艺，工艺集成的复杂性降低。 可以形成内部间隔物或外部隔离物以将基底与发射器隔离。 垫层，本征基层和非本征基层形成具有重合的外侧壁表面的台面结构。

公开(公告)号：US07868423B2

公开(公告)日：2011-01-11

申请号：US12269073

申请日：2008-11-12

Applicant: John J. Benoit ,  David S. Collins ,  Natalie B. Feilchenfeld ,  Michael L. Gautsch ,  Xuefeng Liu ,  Robert M. Rassel ,  Stephen A. St. Onge ,  James A. Slinkman

Inventor： John J. Benoit ,  David S. Collins ,  Natalie B. Feilchenfeld ,  Michael L. Gautsch ,  Xuefeng Liu ,  Robert M. Rassel ,  Stephen A. St. Onge ,  James A. Slinkman

IPC: H01L21/02

CPC classification number: H01L21/761 ,  H01L21/823481 ,  H01L21/823493 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0921 ,  H01L27/0928

Abstract: A structure for a semiconductor device includes an isolated MOSFET (e.g., NFET) having triple-well technology adjacent to an isolated PFET which itself is adjacent to an isolated NFET. The structure includes a substrate in which is formed a deep n-band region underneath any n-wells, p-wells and p-band regions within the substrate. One p-band region is formed above the deep n-band region and underneath the isolated p-well for the isolated MOSFET, while another p-band region is formed above the deep n-band region and underneath all of the p-wells and n-wells, including those that are part of the isolated PFET and NFET devices within the substrate. The n-wells for the isolated MOSFET are connected to the deep n-band region. The resulting structure provides for improved device isolation and reduction of noise propagating from the substrate to the FETs while maintaining the standard CMOS spacing layout spacing rules and electrical biasing characteristics both external and internal to the triple-well isolation regions.

Abstract translation: 用于半导体器件的结构包括具有三阱技术的隔离MOSFET（例如，NFET），其邻近隔离PFET，其本身与隔离的NFET相邻。 该结构包括其中在衬底内的任何n阱，p阱和p带区之下形成深n波段区的衬底。 一个p带区域形成在深n波段区域之上，隔离的MOSFET的隔离p阱下面，而另一个p波段区域形成在深n波段区域之上，并且在所有p-阱区下面， n阱，包括作为衬底内的隔离PFET和NFET器件的一部分的n阱。 隔离MOSFET的n阱连接到深n波段区域。 所得到的结构提供改进的器件隔离和降低从衬底传播到FET的噪声，同时保持三阱隔离区域的外部和内部的标准CMOS间隔布局间隔规则和电偏置特性。

公开(公告)号：US07511940B2

公开(公告)日：2009-03-31

申请号：US11838939

申请日：2007-08-15

Applicant: Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Natalie B. Feilchenfeld ,  Michael L. Gautsch ,  Zhong-Xiang He ,  Matthew D. Moon ,  Vidhya Ramachandran ,  Barbara Waterhouse

Inventor： Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Natalie B. Feilchenfeld ,  Michael L. Gautsch ,  Zhong-Xiang He ,  Matthew D. Moon ,  Vidhya Ramachandran ,  Barbara Waterhouse

IPC: H01G4/38

CPC classification number: H01L23/5223 ,  H01L27/016 ,  H01L27/0805 ,  H01L28/40 ,  H01L2924/0002 ,  Y10T29/49002 ,  H01L2924/00

Abstract: Disclosed is a method of fabricating a metal-insulator-metal (MIM) capacitor. In this method, a dielectric layer is formed above a lower conductor layer and an upper conductor layer is formed above the dielectric layer. The invention then forms an etch stop layer above the upper conductor layer and the dielectric layer, and forms a hardmask (silicon oxide hardmask, a silicon nitride hardmask, etc.) over the etch stop layer. Next, a photoresist is patterned above the hardmask, which allows the hardmask, the etch stop layer, the dielectric layer, and the lower conductor layer to be etched through the photoresist.

Abstract translation: 公开了一种制造金属 - 绝缘体 - 金属（MIM）电容器的方法。 在该方法中，在下导体层的上方形成电介质层，在电介质层的上方形成上导体层。 然后，本发明在上导体层和电介质层之上形成蚀刻停止层，并在蚀刻停止层上形成硬掩模（氧化硅硬掩模，氮化硅硬掩模等）。 接下来，在硬掩模上形成光致抗蚀剂，这允许通过光致抗蚀剂蚀刻硬掩模，蚀刻停止层，电介质层和下导体层。

公开(公告)号：US07301752B2

公开(公告)日：2007-11-27

申请号：US10709907

申请日：2004-06-04

Applicant: Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Natalie B. Feilchenfeld ,  Michael L. Gautsch ,  Zhong-Xiang He ,  Matthew D. Moon ,  Vidhya Ramachandran ,  Barbara Waterhouse

Inventor： Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Natalie B. Feilchenfeld ,  Michael L. Gautsch ,  Zhong-Xiang He ,  Matthew D. Moon ,  Vidhya Ramachandran ,  Barbara Waterhouse

IPC: H01G4/38

CPC classification number: H01L23/5223 ,  H01L27/016 ,  H01L27/0805 ,  H01L28/40 ,  H01L2924/0002 ,  Y10T29/49002 ,  H01L2924/00

Abstract: Disclosed is a method of fabricating a metal-insulator-metal (MIM) capacitor. In this method, a dielectric layer is formed above a lower conductor layer and an upper conductor layer is formed above the dielectric layer. The invention then forms an etch stop layer above the upper conductor layer and the dielectric layer, and forms a hardmask (silicon oxide hardmask, a silicon nitride hardmask, etc.) over the etch stop layer. Next, a photoresist is patterned above the hardmask, which allows the hardmask, the etch stop layer, the dielectric layer, and the lower conductor layer to be etched through the photoresist.

Abstract translation: 公开了一种制造金属 - 绝缘体 - 金属（MIM）电容器的方法。 在该方法中，在下导体层的上方形成电介质层，在电介质层的上方形成上导体层。 然后，本发明在上导体层和电介质层之上形成蚀刻停止层，并在蚀刻停止层上形成硬掩模（氧化硅硬掩模，氮化硅硬掩模等）。 接下来，在硬掩模上形成光致抗蚀剂，这允许通过光致抗蚀剂蚀刻硬掩模，蚀刻停止层，电介质层和下导体层。

公开(公告)号：US06906401B2

公开(公告)日：2005-06-14

申请号：US10856503

申请日：2004-05-28

Applicant: James S. Dunn ,  Natalie B. Feilchenfeld ,  Qizhi Liu ,  Andreas D. Stricker

Inventor： James S. Dunn ,  Natalie B. Feilchenfeld ,  Qizhi Liu ,  Andreas D. Stricker

IPC: H01L21/331 ,  H01L21/8249 ,  H01L29/737 ,  H01L29/72

CPC classification number: H01L29/66242 ,  H01L21/8249 ,  H01L29/7378

Abstract: A method of forming a quasi-self-aligned heterojunction bipolar transistor (HBT) that exhibits high-performance is provided. The method includes the use of a patterned emitter landing pad stack which serves to improve the alignment for the emitter-opening lithography and as an etch stop layer for the emitter opening etch. The present invention also provides an HBT that includes a raised extrinsic base having monocrystalline regions located beneath the emitter landing pad stack.

Abstract translation: 提供了一种形成表现出高性能的准自对准异质结双极晶体管（HBT）的方法。 该方法包括使用图案化的发射器着陆焊盘叠层，其用于改进发射极开口光刻的对准以及用于发射极开口蚀刻的蚀刻停止层。 本发明还提供了一种HBT，其包括具有位于发射器着陆焊盘堆叠下方的单晶区域的凸起的外部基极。

公开(公告)号：US07829945B2

公开(公告)日：2010-11-09

申请号：US11924650

申请日：2007-10-26

Applicant: James W. Adkisson ,  Natalie B. Feilchenfeld ,  Jeffrey P. Gambino ,  Benjamin T. Voegeli ,  Michael J. Zierak

Inventor： James W. Adkisson ,  Natalie B. Feilchenfeld ,  Jeffrey P. Gambino ,  Benjamin T. Voegeli ,  Michael J. Zierak

IPC: H01L21/331

CPC classification number: H01L29/7835 ,  H01L29/1045 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/512 ,  H01L29/66659

Abstract: A gate stack comprising a uniform thickness gate dielectric, a gate electrode, and an oxygen-diffusion-resistant gate cap is formed on a semiconductor substrate. Thermal oxidation is performed only on the drain side of the gate electrode, while the source side is protected from thermal oxidation. A thermal oxide on the drain side sidewall of the gate electrode is integrally formed with a graded thickness silicon oxide containing gate dielectric, of which the thickness monotonically increases from the source side to the drain side. The thickness profile may be self-aligned to the drain side edge of the gate electrode, or may have a portion with a self-limiting thickness. The graded thickness profile may be advantageously used to form a lateral diffusion metal oxide semiconductor field effect transistor providing an enhanced performance.

Abstract translation: 在半导体基板上形成包括均匀厚度的栅极电介质，栅电极和耐氧扩散栅极盖的栅极堆叠。 仅在栅电极的漏极侧进行热氧化，同时防止源极侧受热氧化。 栅电极的漏极侧壁上的热氧化物与层状厚度的含氧化硅的栅极电介质整体形成，其厚度从源极侧向漏极侧单调增加。 厚度分布可以与栅电极的漏极侧边缘自对准，或者可以具有自限制厚度的部分。 梯度厚度分布可以有利地用于形成提供增强性能的横向扩散金属氧化物半导体场效应晶体管。