Method and apparatus for constituting transport network based on integrated synch and asynch frame
    91.
    发明授权
    Method and apparatus for constituting transport network based on integrated synch and asynch frame 有权
    基于集成同步和异步帧构建传输网络的方法和装置

    公开(公告)号:US07843973B2

    公开(公告)日:2010-11-30

    申请号:US11720164

    申请日:2005-11-25

    CPC classification number: H04L12/52 H04L12/64

    Abstract: Provided is a method for forming a customized-quality integrated transport network based on synch and asynch frames, and a transport network forming apparatus thereof. The method of the present invention includes: a) synchronizing a transmission bit rate in a network; b) when the transmission bit rate is synchronized in the network and a connection request is received, establishing a connection by determining a route and a start cycle time of the link based on a quality of the connection request and transporting it to nodes of the link; and c) transmitting data to be transported to a link of an adjacent node within the virtual cycle time when the data are synch frames; or when the data are asynch frames and the data are not transmitted within a virtual cycle time of a link to be switched, keeping the data waiting for a next cycle time.

    Abstract translation: 提供了一种用于形成基于同步和异步帧的定制质量综合传输网络的方法及其传输网络形成装置。 本发明的方法包括:a)使网络中的传输比特率同步; b)当传输比特率在网络中同步并且接收到连接请求时,通过基于连接请求的质量确定链路的路由和开始周期时间来建立连接,并将其传送到链路的节点 ; 以及c)当所述数据是同步帧时,在所述虚拟循环时间内发送要传送的数据到相邻节点的链路; 或者当数据是异步帧并且在要切换的链路的虚拟周期时间内不发送数据时,保持数据等待下一周期时间。

    Lithium secondary battery and a method for preparing the same
    94.
    发明授权
    Lithium secondary battery and a method for preparing the same 有权
    锂二次电池及其制备方法

    公开(公告)号:US07678504B2

    公开(公告)日:2010-03-16

    申请号:US10617811

    申请日:2003-07-14

    Abstract: A lithium secondary battery of the present invention comprises a positive electrode; a negative electrode; a separator interposed between the positive and negative electrodes; and an electrolyte on the separator, wherein the electrolyte includes a non-aqueous organic solvent, a lithium salt, and a linear polymer having P═O bonds. The electrolyte improves the swelling characteristics of lithium secondary batteries. A lithium secondary battery with the electrolyte and a method for preparing the electrolyte and battery is described.

    Abstract translation: 本发明的锂二次电池包括正极; 负极; 插入在正极和负极之间的隔膜; 和隔膜上的电解质,其中所述电解质包括非水有机溶剂,锂盐和具有P = O键的直链聚合物。 电解质改善了锂二次电池的溶胀特性。 描述了具有电解质的锂二次电池和制备电解质和电池的方法。

    Circuit board for a Solenoid Valve Manifold
    96.
    发明申请
    Circuit board for a Solenoid Valve Manifold 有权
    电磁阀歧管电路板

    公开(公告)号:US20090045367A1

    公开(公告)日:2009-02-19

    申请号:US12223736

    申请日:2006-08-04

    Abstract: A circuit board (205) for a valve block (120) of a solenoid valve manifold is described. Each valve block (120) contains a valve which is actuated by either one single solenoid or by two solenoids. Both sides (210, 220) of the circuit board (210) are provided with a circuit (212, 222). The first surface (210) of the circuit board (205) carries a single type valve circuit (212) for supplying one single solenoid with electrical energy. This first surface (210) can be mark e.g. with an “S”. The second surface (220) of the circuit board (205) carries a double-type valve circuit (222) for supplying two solenoids with electrical power. This second surface (220) can be marked e.g. with a “D”. The circuit board (205) is positioned in the respective valve block (120) with the first surface (210) or the second surface (220) facing upwards depending on whether a single- or a double-solenoid-valve is used in the respective valve block (120).

    Abstract translation: 描述了用于电磁阀歧管的阀块(120)的电路板(205)。 每个阀块(120)包含由一个单个螺线管或两个螺线管致动的阀。 电路板(210)的两侧(210,220)设置有电路(212,222)。 电路板(205)的第一表面(210)承载用于向单个螺线管提供电能的单一型阀电路(212)。 该第一表面(210)可以标记为例如。 带有“S”。 电路板(205)的第二表面(220)承载用于向两个螺线管供电的双电源电路(222)。 该第二表面(220)可以被标记为例如。 带有“D”。 电路板(205)位于相应的阀块(120)中,其中第一表面(210)或第二表面(220)面向上,这取决于在相应的方法中是使用单电磁阀还是双电磁阀 阀块(120)。

    Method and Apparatus for Constituting Transport Network Based on Integrated Synch and Asynch Frame
    97.
    发明申请
    Method and Apparatus for Constituting Transport Network Based on Integrated Synch and Asynch Frame 有权
    基于集成同步和异步帧构建传输网络的方法和装置

    公开(公告)号:US20080107136A1

    公开(公告)日:2008-05-08

    申请号:US11720164

    申请日:2005-11-25

    CPC classification number: H04L12/52 H04L12/64

    Abstract: Provided is a method for forming a customized-quality integrated transport network based on synch and asynch frames, and a transport network forming apparatus thereof. The method of the present invention includes: a) synchronizing a transmission bit rate in a network; b) when the transmission bit rate is synchronized in the network and a connection request is received, establishing a connection by determining a route and a start cycle time of the link based on a quality of the connection request and transporting it to nodes of the link; and c) transmitting data to be transported to a link of an adjacent node within the virtual cycle time when the data are synch frames; or when the data are asynch frames and the data are not transmitted within a virtual cycle time of a link to be switched, keeping the data waiting for a next cycle time.

    Abstract translation: 提供了一种用于形成基于同步和异步帧的定制质量综合传输网络的方法及其传输网络形成装置。 本发明的方法包括:a)使网络中的传输比特率同步; b)当传输比特率在网络中同步并且接收到连接请求时,通过基于连接请求的质量确定链路的路由和开始周期时间来建立连接,并将其传送到链路的节点 ; 以及c)当所述数据是同步帧时,在所述虚拟循环时间内发送要传送的数据到相邻节点的链路; 或者当数据是异步帧并且在要切换的链路的虚拟周期时间内不发送数据时,保持数据等待下一周期时间。

    Semiconductor memory device and a reading method thereof
    99.
    发明授权
    Semiconductor memory device and a reading method thereof 失效
    半导体存储器件及其读取方法

    公开(公告)号:US5883851A

    公开(公告)日:1999-03-16

    申请号:US44396

    申请日:1998-03-18

    Applicant: Jin-Young Lee

    Inventor: Jin-Young Lee

    CPC classification number: G11C7/1048 G11C7/06 G11C7/22 G11C8/18

    Abstract: In a semiconductor memory device, there is provided a column detecting circuit for generating a detection signal DETIO when respective voltage levels on a pair of I/O lines IO and IOB are developed into predetermined voltage levels which can be sensed as a valid data by external circuitry. Thereafter, a block selecting circuit and a sensing control signal generating circuit are respectively disabled by the detection signals DETIO and DETIOB causing a bit line precharge operation to be performed during a reading operation Thus, the sensing consumed by sense amplifiers during the reading operation period is reduced. In addition, since the bit line precharge operation is performed during the reading operation period, the bit line precharge time is reduced.

    Abstract translation: 在半导体存储器件中,提供一个列检测电路,用于当一对I / O线IO和IOB上的各个电压电平发展成预定的电压电平时,用于产生检测信号DETIO,该电压电平可通过外部检测为有效数据 电路。 此后,通过检测信号DETIO和DETIOB分别禁止块选择电路和感测控制信号发生电路,从而在读取操作期间执行位线预充电操作。因此,读取操作期间读出放大器消耗的感测是 减少 此外,由于在读取操作期间执行位线预充电操作,所以位线预充电时间减少。

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