公开(公告)号：US07166013B2

公开(公告)日：2007-01-23

申请号：US11004991

申请日：2004-12-07

Applicant: Shigeo Moriyama ,  Yoshihiro Ishida ,  Takashi Kugaya ,  Shigeo Ootsuki ,  Soichi Katagiri ,  Sadayuki Nishimura ,  Ryosei Kawai ,  Kan Yasui

Inventor： Shigeo Moriyama ,  Yoshihiro Ishida ,  Takashi Kugaya ,  Shigeo Ootsuki ,  Soichi Katagiri ,  Sadayuki Nishimura ,  Ryosei Kawai ,  Kan Yasui

IPC: B24B49/00 ,  B24B51/00 ,  B24B1/00 ,  B24B29/00

CPC classification number: B24B53/017 ,  B24B37/042 ,  B24B41/04 ,  B24B53/12

Abstract: The present invention relates to a polishing apparatus, and a semiconductor manufacturing method using the apparatus. Dressing of a grindstone surface is ground by sizing processing whereby dressing of a tool surface can be done while preventing occurrence of cracks on the grindstone surface which is the cause for occurrence of scratches. Further, flatness of the surface of a dressing tool can be guaranteed because of sizing cutting-in; even if a thick grindstone of a few centimeters is used, the flatness can be maintained to the end; and processing with less in-face unevenness can be always carried out. Therefore, the life of the dressing tool can be greatly extended.Further, the present sizing-dressing is carried out jointly with processing of a wafer to thereby enable improvement of throughput of the apparatus as well as maintenance of a processing rate.The present apparatus and method are effective for planarization of various substrate surfaces having irregularities.

Abstract translation: 本发明涉及一种抛光装置以及使用该装置的半导体制造方法。 磨石表面的磨合通过施胶处理进行研磨，由此可以进行工具表面的修整，同时防止在磨石表面产生裂纹，这是产生划痕的原因。 此外，可以保证修整工具的表面的平整度，因为切割的尺寸大小; 即使使用了几厘米厚的砂轮，也可以保持平坦度， 并且可以总是执行具有较少的面内不均匀性的处理。 因此，修整工具的寿命可以大大延长。 此外，与晶片的处理联合进行本施胶修整，从而能够提高装置的生产量以及维持处理速度。 本装置和方法对于具有不规则性的各种衬底表面的平坦化是有效的。

公开(公告)号：US07085157B2

公开(公告)日：2006-08-01

申请号：US10805365

申请日：2004-03-22

Applicant: Toshihiro Tanaka ,  Takashi Yamaki ,  Yutaka Shinagawa ,  Daisuke Okada ,  Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru

Inventor： Toshihiro Tanaka ,  Takashi Yamaki ,  Yutaka Shinagawa ,  Daisuke Okada ,  Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru

IPC: G11C11/34 ,  G11C16/04

CPC classification number: G11C16/10 ,  G11C16/0433

Abstract: A method for speeding up data writing and reducing power consumption by reducing the variation of the threshold voltage of each of non-volatile memory cells at data writing. When writing data in a memory cell, a voltage of about 8V is applied to the memory gate line, a voltage of about 5V is applied to the source line, a voltage of about 1.5V is applied to the selected gate line respectively. At that time, in the writing circuit, the writing pulse is 0, the writing latch output a High signal, and a NAND-circuit outputs a Low signal. And, a constant current of about 1 ìA flows in a constant current source transistor and the bit line is discharged by a constant current of about 1 ìA to flow a current in the memory cell.

Abstract translation: 一种用于通过在数据写入时减小每个非易失性存储单元的阈值电压的变化来加速数据写入和降低功耗的方法。 当在存储单元中写入数据时，约8V的电压被施加到存储器栅极线，大约5V的电压被施加到源极线，大约1.5V的电压分别施加到所选择的栅极线。 此时，在写入电路中，写入脉冲为0，写入锁存器输出高电平信号，NAND电路输出低电平信号。 并且，在恒定电流源晶体管中流动约1AA的恒定电流，并且通过约1μA的恒定电流放电位线以使存储器单元中的电流流动。

公开(公告)号：US20060057940A1

公开(公告)日：2006-03-16

申请号：US11267306

申请日：2005-11-07

Applicant: Shigeo Moriyama ,  Yoshihiro Ishida ,  Takashi Kugaya ,  Shigeo Ootsuki ,  Soichi Katagiri ,  Sadayuki Nishimura ,  Ryosei Kawai ,  Kan Yasui

Inventor： Shigeo Moriyama ,  Yoshihiro Ishida ,  Takashi Kugaya ,  Shigeo Ootsuki ,  Soichi Katagiri ,  Sadayuki Nishimura ,  Ryosei Kawai ,  Kan Yasui

IPC: B24B51/00 ,  B24B7/30 ,  B24B1/00 ,  B24B29/00 ,  B24B21/18

CPC classification number: B24B53/017 ,  B24B37/042 ,  B24B41/04 ,  B24B53/02 ,  B24B53/12

Abstract: The present invention relates to a polishing apparatus, and a semiconductor manufacturing method using the apparatus. Dressing of a grindstone surface is ground by sizing processing whereby dressing of a tool surface can be done while preventing occurrence of cracks on the grindstone surface which is the cause for occurrence of scratches. Further, flatness of the surface of a dressing tool can be guaranteed because of sizing cutting-in; even if a thick grindstone of a few centimeters is used, the flatness can be maintained to the end; and processing with less in-face unevenness can be always carried out. Therefore, the life of the dressing tool can be greatly extended. Further, the present sizing-dressing is carried out jointly with processing of a wafer to thereby enable improvement of throughput of the apparatus as well as maintenance of a processing rate. The present apparatus and method are effective for planarization of various substrate surfaces having irregularities.

公开(公告)号：US06849542B2

公开(公告)日：2005-02-01

申请号：US10272831

申请日：2002-10-18

Applicant: Soichi Katagiri ,  Ui Yamaguchi ,  Seiichi Kondo ,  Kan Yasui ,  Masahiro Kaise ,  Minoru Honda

Inventor： Soichi Katagiri ,  Ui Yamaguchi ,  Seiichi Kondo ,  Kan Yasui ,  Masahiro Kaise ,  Minoru Honda

IPC: B24B57/02 ,  B24D3/32 ,  B24D3/34 ,  B24D7/06 ,  H01L21/304 ,  H01L21/321 ,  H01L21/463

CPC classification number: B24B37/245 ,  B24B37/042 ,  B24B37/22 ,  B24B57/02 ,  B24D3/32 ,  B24D3/344 ,  B24D7/063 ,  H01L21/3212

Abstract: The invention provides a method for manufacturing a semiconductor device with reduced dishing and erosion. In this method for manufacturing a semiconductor device, the convex/concave pattern is planarized by relatively moving a substrate having the convex/concave pattern on the surface and a polishing tool with pressing the convex/concave surface of the substrate on the polishing tool. The polishing tool is provided with a grindstone 10 having a plurality of polygonal segments 20, which comprises abrasive 23 that is bonded together with resin 24 and contains pores 22. The polygonal segments are arranged so that corners of three or more polygonal segments are not located near each other.

Abstract translation: 本发明提供一种制造具有减少的凹陷和侵蚀的半导体器件的方法。 在这种制造半导体器件的方法中，通过在表面上相对移动具有凸/凹图案的衬底和将抛光工具上的衬底的凸/凹表面压在一起的抛光工具，使凸/凹图案平坦化。 抛光工具设置有具有多个多边形节段20的磨石10，磨石10包括与树脂24结合并包含孔22的磨料23。多边形节段被布置成使得三个或更多个多边形节段的角部不位于 靠近对方

公开(公告)号：US06777337B2

公开(公告)日：2004-08-17

申请号：US09910904

申请日：2001-07-24

Applicant: Kan Yasui ,  Souichi Katagiri ,  Masayuki Nagasawa ,  Ui Yamaguchi ,  Yoshio Kawamura

Inventor： Kan Yasui ,  Souichi Katagiri ,  Masayuki Nagasawa ,  Ui Yamaguchi ,  Yoshio Kawamura

IPC: H01L21302

CPC classification number: B24B37/042 ,  H01L21/31053

Abstract: In a production process of a semiconductor device, planarizing of a wafer surface pattern can be performed to attain high planarity, good uniformity in the removal amount and improved controllability. This process include a step of planarizing a semiconductor wafer, from which at least two different films have been exposed, by polishing with a grindstone and a dispersant-containing processing liquid.

Abstract translation: 在半导体装置的制造方法中，可以进行晶片表面图案的平坦化，以获得高的平坦度，良好的去除量均匀性和改进的可控性。 该方法包括通过用磨石和含分散剂处理液进行抛光来平坦化半导体晶片的步骤，从半导体晶片至少暴露出两个不同的膜。

公开(公告)号：US06734103B2

公开(公告)日：2004-05-11

申请号：US10081212

申请日：2002-02-25

Applicant: Souichi Katagiri ,  Ui Yamaguchi ,  Seiichi Kondo ,  Kan Yasui ,  Yoshio Kawamura

Inventor： Souichi Katagiri ,  Ui Yamaguchi ,  Seiichi Kondo ,  Kan Yasui ,  Yoshio Kawamura

IPC: H01L21302

CPC classification number: B24B7/228 ,  B24B53/02 ,  C23F3/00 ,  H01L21/3212 ,  H01L21/7684

Abstract: A method of manufacturing is described wherein a semiconductor device has a substrate as workpiece with an insulation film formed on the substrate, openings formed inside the insulation film, a first conductive film is formed inside the openings and on a surface of the insulation film, a second conductive film is formed on the first conductive film, and the first and the second conductive films are formed inside openings by planarizing a surface of second conductive film and a surface part of the first conductive film with a fixed abrasive tool. The method includes supplying a first processing liquid, planarizing the surface of the second conductive film with the first processing liquid and the fixed abrasive tool, switching the supply of liquid from a first processing liquid to a second processing liquid, and planarizing the surface of second conductive film and the surface of part of the first conductive film with the second processing liquid and the fixed abrasive tool.

Abstract translation: 描述了一种制造方法，其中半导体器件具有作为工件的基板，在基板上形成绝缘膜，形成在绝缘膜内部的开口，第一导电膜形成在开口内部和绝缘膜的表面上， 第二导电膜形成在第一导电膜上，并且通过用固定的研磨工具平面化第二导电膜的表面和第一导电膜的表面部分，在开口内形成第一和第二导电膜。 该方法包括提供第一处理液体，将第二导电膜的表面与第一处理液体和固定研磨工具平坦化，将液体从第一处理液体切换到第二处理液体，并将第二处理液体的表面平坦化 导电膜和第一导电膜的部分表面与第二处理液和固定研磨工具。

公开(公告)号：US06676496B2

公开(公告)日：2004-01-13

申请号：US09835359

申请日：2001-04-17

Applicant: Kan Yasui ,  Shigeo Moriyama ,  Katsuhiko Yamaguchi ,  Yoshio Homma

Inventor： Kan Yasui ,  Shigeo Moriyama ,  Katsuhiko Yamaguchi ,  Yoshio Homma

IPC: B24B100

CPC classification number: B24B37/04 ,  B24B57/02

Abstract: A method for processing semiconductor wafers, which provides planarized surface in a well controllable manner and with high accuracy by processing a film with uneven surface, formed over a semiconductor wafer, within the area of a working surface with a diameter larger than that of said semiconductor wafer by not more than two times, and by processing the film with a polishing liquid supplied from a supply unit disposed on a vertically arranged working surface is disclosed. Additionally, high quality dressing of the working surface can be easily performed by virtue of the smaller diameter of the working surface. Furthermore, the vertical arrangement of the working surface makes possible ready compatibility with semiconductor wafers of enlarged diameters.

Abstract translation: 一种用于处理半导体晶片的方法，其在工作表面的直径大于所述半导体的直径的区域内，以半导体晶片形成在半导体晶片上，通过处理具有不平坦表面的膜，以良好可控的方式并且以高精度提供平坦化表面 晶片不超过两次，并且通过用设置在垂直布置的工作表面上的供应单元供应的抛光液处理该膜。 此外，通过工作表面的较小直径，可以容​​易地进行工作表面的高质量的修整。 此外，工作表面的垂直布置使得可以准确地兼容扩大直径的半导体晶片。

公开(公告)号：US06663468B2

公开(公告)日：2003-12-16

申请号：US09754193

申请日：2001-01-05

Applicant: Yoshio Kawamura ,  Kan Yasui ,  Masahiko Sato ,  Souichi Katagiri ,  Masayuki Nagasawa ,  Kunio Harada ,  Satoshi Osabe ,  Ui Yamaguchi

Inventor： Yoshio Kawamura ,  Kan Yasui ,  Masahiko Sato ,  Souichi Katagiri ,  Masayuki Nagasawa ,  Kunio Harada ,  Satoshi Osabe ,  Ui Yamaguchi

IPC: B24B100

CPC classification number: B24B37/32 ,  H01L21/31053 ,  H01L21/3212

Abstract: The problem of non-uniform polishing properties of a circumferential surface area of a substrate, so-called edge sagging phenomenon, is solved. When a thin film formed on a top surface of the substrate is polished while holding a back surface of the substrate, local stress at a circumferential end of the substrate is reduced by a guide installed so as to surround the substrate. Also, a deformation of the outer circumferential end portion of the substrate is reduced by a recessed groove provided on the guide. Since a thin film formed on the surface can be polished to be flat throughout the surface of the substrate without an occurrence of non-uniform polishing properties of the outer circumferential surface area of the substrate, so-called edge sagging phenomenon, a high-performance semiconductor device can be manufactured at a high yield and low costs.

Abstract translation: 解决了基板的圆周表面积的不均匀抛光性能，所谓的边缘下垂现象的问题。 当在保持基板的后表面的同时抛光形成在基板的顶表面上的薄膜时，通过安装成围绕基板的引导件来减小基板周向端部的局部应力。 此外，通过设置在引导件上的凹槽来减小基板的外周端部的变形。 由于形成在表面上的薄膜可以在基板的整个表面上被抛光成平坦的，而不会发生基板的外周表面积的不均匀的抛光性能，所谓的边缘下垂现象，高性能 可以以高产率和低成本制造半导体器件。

公开(公告)号：US06565424B2

公开(公告)日：2003-05-20

申请号：US09863264

申请日：2001-05-24

Applicant: Souichi Katagiri ,  Yoshio Kawamura ,  Kan Yasui ,  Masayuki Nagasawa ,  Ui Yamaguchi

Inventor： Souichi Katagiri ,  Yoshio Kawamura ,  Kan Yasui ,  Masayuki Nagasawa ,  Ui Yamaguchi

IPC: B24B100

CPC classification number: B24B37/30 ,  B24B37/042 ,  B24B37/32

Abstract: The invention provides a process apparatus including a wafer holder, and a process method, in which high planarization performance, scratch free process, narrow edge exclusion and high uniformity can be maintained for more than 10,000 processed wafers. The invention is achieved by providing a unit for keeping a retainer and surface of a polishing wheel non-contact with each other and controlling the gap within a certain range and by setting compression strength of the retainer at more than 3,000 kg/cm2.

公开(公告)号：US06390895B1

公开(公告)日：2002-05-21

申请号：US09634740

申请日：2000-08-08

Applicant: Souichi Katagiri ,  Kan Yasui

Inventor： Souichi Katagiri ,  Kan Yasui

IPC: B24B100

CPC classification number: B24B53/017

Abstract: With a time control means for a wetting treatment of a fixed abrasive platen provided, the fixed abrasive platen is set in a good wet state in advance prior to the start of polishing. The time control means may be incorporated in the body of a flattening/machining apparatus, or alternatively a wetting retaining mean may newly be separately provided instead. While the fixed abrasive platen is rapidly transformed through expansion due to wetting, the wetting treatment is desirably performed till a transformation ratio thereof is stabilized at 0.0005% or less.