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    Nonvolatile memory device, memory system comprising nonvolatile memory device, and wear leveling method for nonvolatile memory device
    92.
    发明授权
    Nonvolatile memory device, memory system comprising nonvolatile memory device, and wear leveling method for nonvolatile memory device 有权
    非易失性存储器件，包括非易失性存储器件的存储器系统和用于非易失性存储器件的磨损均衡方法

    公开(公告)号：US08495283B2

    公开(公告)日：2013-07-23

    申请号：US12947003

    申请日：2010-11-16

    Applicant: Min Gun Park ,  Ki Tae Park

    Inventor： Min Gun Park ,  Ki Tae Park

    IPC: G06F12/00

    CPC classification number: G06F12/0246 ,  G06F2212/7211 ,  G11C7/04 ,  G11C13/0035 ,  G11C16/26 ,  G11C16/349

    Abstract: A nonvolatile memory device comprises a memory core and a controller for controlling the wear level of a memory block in the nonvolatile memory device. The controller determines the wear level of a memory block by obtaining data of an actual wear level from a charge measurement cell of a selected region of the memory cell, and stores the wear level of the selected region in an erase count table.

    Abstract translation: 非易失性存储器件包括存储器核心和用于控制非易失性存储器件中的存储器块的磨损水平的控制器。 控制器通过从存储单元的选定区域的电荷测量单元获取实际的磨损水平的数据来确定存储器块的磨损水平，并将所选区域的磨损水平存储在擦除计数表中。

    Micro manipulator for electrode movement in neural signal recording
    93.
    发明授权
    Micro manipulator for electrode movement in neural signal recording 有权
    微机械手用于神经信号记录中的电极运动

    公开(公告)号：US08435250B2

    公开(公告)日：2013-05-07

    申请号：US12541558

    申请日：2009-08-14

    Applicant: Eui Sung Yoon ,  Sung Wook Yang ,  Jin Seok Kim ,  Duk Moon Rho ,  Ki Tae Park ,  Se Min Lee ,  Jei Won Cho ,  Hee Sup Shin

    Inventor： Eui Sung Yoon ,  Sung Wook Yang ,  Jin Seok Kim ,  Duk Moon Rho ,  Ki Tae Park ,  Se Min Lee ,  Jei Won Cho ,  Hee Sup Shin

    IPC: A61B19/00

    CPC classification number: A61N1/0529 ,  A61B5/0051 ,  A61B5/04001 ,  A61B5/065 ,  A61B90/11 ,  A61B2017/00398 ,  A61B2034/2051

    Abstract: This disclosure relates to a micro manipulator having a simple structure and having high possibility of recording a biological signal of a neuron at a desired position by improving positioning resolution of an electrode disposed adjacent to a subject's brain neuron or an electrode holder attached with the electrode. The micro manipulator according to the disclosure includes: a motor which includes a shaft and a vibration portion; a mobile which is connected to the shaft so as to be movable along the shaft; and a frame which supports the motor, wherein an electrode is connected to the mobile in a direction parallel to a longitudinal direction of the shaft, and wherein when the mobile moves linearly in accordance with a vibration of the shaft due to the vibration portion, the electrode moves linearly.

    Abstract translation: 本公开涉及一种具有简单结构的微操纵器，并且通过改善与被检体的脑神经元邻近设置的电极的定位分辨率或与电极连接的电极保持器，可以将希望位置处的神经元的生物信号记录到高可能性。 根据本公开的微机械手包括：电动机，其包括轴和振动部分; 移动体，其连接到所述轴，以便能够沿着所述轴移动; 以及支撑电动机的框架，其中电极在与轴的纵向方向平行的方向上连接到移动体，并且其中当移动体根据由于振动部分的轴的振动而线性移动时， 电极线性移动。

    NONVOLATILE MEMORY DEVICE PROVIDING NEGATIVE VOLTAGE
    95.
    发明申请
    NONVOLATILE MEMORY DEVICE PROVIDING NEGATIVE VOLTAGE 有权
    提供负电压的非易失性存储器件

    公开(公告)号：US20130010539A1

    公开(公告)日：2013-01-10

    申请号：US13463063

    申请日：2012-05-03

    Applicant: Sang-Won Shim ,  Pan-Suk Kwak ,  Ki-Tae Park ,  Yoon-Hee Choi

    Inventor： Sang-Won Shim ,  Pan-Suk Kwak ,  Ki-Tae Park ,  Yoon-Hee Choi

    IPC: G11C16/04

    CPC classification number: G11C16/0433 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/30

    Abstract: Disclosed is a nonvolatile memory device which includes memory blocks, a pre-decoder, and a row decoder. Each of the memory blocks has a plurality of memory cells. The pre-decoder includes a multiplexer and negative level shifters. The multiplexer is configured to generate multiplexing signals in response to address signals. Each of the negative level shifters is configured to generate a converted multiplexing signal corresponding to a respective multiplexing signal by converting a multiplexing signal having a ground voltage into a converted multiplexing signal having a first negative voltage. The row decoder is configured to select at least one of the memory blocks in response to the converted multiplexing signals.

    Abstract translation: 公开了一种非易失性存储器件，其包括存储器块，预解码器和行解码器。 每个存储块具有多个存储单元。 预解码器包括多路复用器和负电平移位器。 复用器被配置为响应于地址信号产生复用信号。 每个负电平移位器被配置为通过将具有接地电压的多路复用信号转换成具有第一负电压的转换多路复用信号来生成与各个多路复用信号相对应的转换的复用信号。 行解码器被配置为响应于转换的复用信号来选择至少一个存储器块。

    Flash memory device configured to reduce common source line noise, methods of operating same, and memory system incorporating same
    97.
    发明授权
    Flash memory device configured to reduce common source line noise, methods of operating same, and memory system incorporating same 有权
    闪存设备被配置为减少公共源线噪声，操作方法，以及并入其的存储器系统

    公开(公告)号：US08264888B2

    公开(公告)日：2012-09-11

    申请号：US12838584

    申请日：2010-07-19

    Applicant: Yoon-Hee Choi ,  Ki tae Park ,  Bo Geun Kim

    Inventor： Yoon-Hee Choi ,  Ki tae Park ,  Bo Geun Kim

    IPC: G11C16/04 ,  G11C16/06

    CPC classification number: G11C16/3468 ,  G11C16/0483 ,  G11C16/10

    Abstract: A flash memory device comprises memory cells connected between a bit line and a common source line, word lines connected to the memory cells, a common source line feedback circuit connected to a common source line (CSL) to detect the voltage level of the common source line, and a CSL feedback control logic configured to control a voltage level of a selected word line or a selected bit line to be compensated to a substantially constant value during a sensing operation of the memory cells based on the detected voltage level of the CSL.

    Abstract translation: 闪存器件包括连接在位线和公共源极线之间的存储器单元，连接到存储器单元的字线，连接到公共源极线（CSL）的公共源极线反馈电路，以检测公共源极的电压电平 线路和CSL反馈控制逻辑，其配置成在所述存储器单元的感测操作期间基于所述检测到的所述CSL的电压电平来将所选择的字线或所选择的位线的电压电平控制为基本上恒定的值。

    NAND flash memory device having dummy memory cells and methods of operating same
    98.
    发明授权
    NAND flash memory device having dummy memory cells and methods of operating same 有权
    具有虚拟存储单元的NAND闪存器件及其操作方法

    公开(公告)号：US08228738B2

    公开(公告)日：2012-07-24

    申请号：US12977419

    申请日：2010-12-23

    Applicant: Ki-Tae Park ,  Jung-Dal Choi ,  Jong-Sun Sel ,  Yoo-Cheol Shin

    Inventor： Ki-Tae Park ,  Jung-Dal Choi ,  Jong-Sun Sel ,  Yoo-Cheol Shin

    IPC: G11C16/04 ,  G11C16/06 ,  G11C16/10

    CPC classification number: G11C16/0483 ,  G11C16/107 ,  G11C16/12 ,  G11C16/3445

    Abstract: A NAND flash memory device includes a control circuit configured to apply, during a program operation, a first word line voltage to non-selected ones of a plurality of serially-connected memory cells, a second word line voltage greater than the first word line voltage to a selected one of the plurality of memory cells, and a third word line voltage lower than the first word line voltage to a dummy memory cell connected in series with the plurality of memory cells. In other embodiments, a control circuit is configured to program a dummy memory cell before and/or after each erase operation on a plurality of memory cells connected in series therewith. In still other embodiments, a control circuit is configured to forego erasure of a dummy memory cell while erasing a plurality of memory cells connected in series therewith.

    Abstract translation: NAND闪速存储器件包括控制电路，其被配置为在编程操作期间将第一字线电压施加到多个串联存储器单元中的未选择的电压，第二字线电压大于第一字线电压 到多个存储单元中的一个选择的一个，以及比第一字线电压低的第三字线电压到与多个存储单元串联连接的虚拟存储单元。 在其他实施例中，控制电路被配置为在与每个擦除操作之间的每个擦除操作之前和/或之后对与其串联的多个存储器单元进行编程。 在其他实施例中，控制电路被配置为在擦除与其串联连接的多个存储器单元时，放弃擦除伪存储器单元。

    Memory device and operating method
    99.
    发明授权
    Memory device and operating method 有权
    内存设备和操作方法

    公开(公告)号：US08194449B2

    公开(公告)日：2012-06-05

    申请号：US12647583

    申请日：2009-12-28

    Applicant: Ki Tae Park

    Inventor： Ki Tae Park

    IPC: G11C16/04

    CPC classification number: G11C16/26 ,  G11C16/0483

    Abstract: A method of operating a memory device includes; defining a plurality of read levels, using the plurality of read levels to determine electrical property differences between first and second memory cells adjacent dispose along a common word line, and determining read data stored in the first and second memory cells in relation to the determination of electrical property differences between the first and second memory cells.

    Abstract translation: 操作存储器件的方法包括： 定义多个读取电平，使用所述多个读取电平来确定沿着公共字线相邻布置的第一和第二存储器单元之间的电特性差异，以及确定存储在所述第一和第二存储器单元中的读取数据与 第一和第二存储单元之间的电性能差异。

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