公开(公告)号：US20100131724A1

公开(公告)日：2010-05-27

申请号：US12597097

申请日：2008-04-25

申请人： Seiji Miura ,  Yoshinori Haraguchi ,  Kazuhiko Abe ,  Shoji Kaneko

发明人： Seiji Miura ,  Yoshinori Haraguchi ,  Kazuhiko Abe ,  Shoji Kaneko

IPC分类号： G06F12/00 ,  G11C7/00 ,  G11C8/16

CPC分类号： G11C14/00 ,  G06F13/4243 ,  G11C16/30

摘要： The present invention has an object of providing a high-speed, low-cost, and user-friendly information processing system that can ensure scalability of memory capacity. The information processing system is configured to include an information processing device, a volatile memory, and a nonvolatile memory. By serially connecting the information processing device, the volatile memory, and the nonvolatile memory and reducing the number of connection signals, processing speed is increased while maintaining the scalability of memory capacity. When transferring data of the nonvolatile memory to the volatile memory, error correction is performed, thereby improving reliability. The information processing system including the plurality of chips is configured as an information-processing system module in which the chips are alternately stacked and arranged, and wired by a ball grid array (BGA) or by bonding between the chips.

摘要翻译： 本发明的目的是提供一种高速，低成本和用户友好的信息处理系统，其可以确保存储器容量的可扩展性。 信息处理系统被配置为包括信息处理设备，易失性存储器和非易失性存储器。 通过串行连接信息处理装置，易失性存储器和非易失性存储器并减少连接信号的数量，提高处理速度，同时保持存储容量的可扩展性。 当将非易失性存储器的数据传送到易失性存储器时，执行错误校正，从而提高可靠性。 包括多个芯片的信息处理系统被配置为信息处理系统模块，其中芯片被交替堆叠和布置，并且由球栅阵列（BGA）或芯片之间的接合进行布线。

公开(公告)号：US07624238B2

公开(公告)日：2009-11-24

申请号：US11453907

申请日：2006-06-16

申请人： Seiji Miura ,  Kazushige Ayukawa

发明人： Seiji Miura ,  Kazushige Ayukawa

IPC分类号： G06F12/00

CPC分类号： G06F13/161 ,  G06F12/0215 ,  G11C7/1018 ,  Y02D10/13 ,  Y02D10/14

摘要： A memory controller and data processor have their operation mode switched from the page-on mode for high-speed access to a same page to the page-off mode in response to consecutive events of access to different pages, so that the memory access is performed at a high speed and low power consumption.

公开(公告)号：US20090245004A1

公开(公告)日：2009-10-01

申请号：US12482579

申请日：2009-06-11

申请人： Kazushige Ayukawa ,  Seiji Miura ,  Yoshikazu Saitou

发明人： Kazushige Ayukawa ,  Seiji Miura ,  Yoshikazu Saitou

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C11/005 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C5/143 ,  G11C8/12 ,  G11C11/406 ,  G11C11/40607 ,  G11C11/40618 ,  G11C11/4076 ,  H01L2224/06145 ,  H01L2224/06156 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48227 ,  H01L2924/01039 ,  H01L2924/01055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00

摘要： In order to implement a memory having a large storage capacity and a reduced data retention current, a non-volatile memory, an SRAM, a DRAM, and a control circuit are modularized into one package. The control circuit conducts assignment of addresses to the SRAM and DRAM, and stores data that must be retained over a long period of time in the SRAM. In the DRAM, a plurality of banks are divided into two sets, and mapped to the same address space, and sets are refreshed alternately. A plurality of chips of them are stacked and disposed, and wired by using the BGA and chip-to-chip bonding.

摘要翻译： 为了实现具有大的存储容量和减少的数据保持电流的存储器，非易失性存储器，SRAM，DRAM和控制电路被模块化成一个封装。 控制电路对SRAM和DRAM进行地址分配，并将要长时间保留的数据存储在SRAM中。 在DRAM中，多个存储体被分成两组，映射到相同的地址空间，并且交替地刷新集合。 它们的多个芯片被堆叠和布置，并且通过使用BGA和芯片到芯片的接合进行布线。

公开(公告)号：US20090138624A1

公开(公告)日：2009-05-28

申请号：US12276143

申请日：2008-11-21

申请人： Roger Dwain ISAAC ,  Seiji MIURA

发明人： Roger Dwain ISAAC ,  Seiji MIURA

IPC分类号： G06F13/00 ,  G06F13/28 ,  G06F13/14 ,  G06F3/00 ,  G06F13/37

CPC分类号： G06F13/1673 ,  G06F13/1684

摘要： Efficient and convenient storage systems and methods are presented. In one embodiment a storage system includes a plurality of storage nodes and a master controller. The storage nodes store information. The storage node includes an upstream communication buffer which is locally controlled at the storage node to facilitate resolution of conflicts in upstream communications. The master controller controlls the flow of traffic to the node based upon constraints of the upstream communication buffer. In one embodiment, communication between the master controller and the node has a determined maximum latency. The storage node can be coupled to the master controller in accordance with a chain memory configuration.

摘要翻译： 介绍了高效便捷的存储系统和方法。 在一个实施例中，存储系统包括多个存储节点和主控制器。 存储节点存储信息。 存储节点包括在存储节点处本地控制的上游通信缓冲器，以便于解决上游通信中的冲突。 主控制器基于上游通信缓冲器的约束来控制到节点的流量流。 在一个实施例中，主控制器和节点之间的通信具有确定的最大等待时间。 存储节点可以根据链式存储器配置耦合到主控制器。

公开(公告)号：US20080245808A1

公开(公告)日：2008-10-09

申请号：US11872512

申请日：2007-10-15

申请人： Kouji SAKOTA ,  Seiji MIURA

发明人： Kouji SAKOTA ,  Seiji MIURA

IPC分类号： B65G47/00

CPC分类号： B23P19/007 ,  B23K11/0053 ,  B23K11/36

摘要： A small-diameter front-end portion of a feed rod is allowed to enter into the screw hole of a nut delivered by a nut chute, and the nut is fed to an intended position by the forward movement of the feed rod. When an abnormal nut having a screw hole into which the small-diameter front-end portion cannot be inserted is delivered, the abnormal nut is prevented from being flicked by the feed rod. In order to achieve this, in a standby state, the small-diameter front-end portion of the feed rod enters a nut receiving chamber and is then stopped. On condition that the abnormal nut is received in the nut receiving chamber, if the feed rod moves forward to enter into the standby state, the abnormal nut is slightly pushed out forward from the nut receiving chamber.

摘要翻译： 进给杆的小直径前端部分被允许进入由螺母滑槽输送的螺母的螺孔中，并且通过进给杆的向前运动将螺母进给到预期位置。 当具有不能插入小直径前端部分的螺孔的异常螺母被输送时，防止异常螺母被进给杆弹起。 为了实现这一点，在待机状态下，进给棒的小直径前端部分进入螺母接收室，然后停止。 在螺母接收室中接收到异常螺母的情况下，如果进给杆向前移动进入待机状态，则异常螺母稍微从螺母接收室向前推出。

公开(公告)号：US07280426B2

公开(公告)日：2007-10-09

申请号：US11439139

申请日：2006-05-24

申请人： Seiji Miura ,  Kazushige Ayukawa

发明人： Seiji Miura ,  Kazushige Ayukawa

IPC分类号： G11C8/00 ,  G11C7/00

CPC分类号： G06F12/0246 ,  G11C5/02 ,  G11C5/025 ,  G11C5/04 ,  G11C11/005 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/40607 ,  G11C11/412 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C29/70

摘要： A semiconductor device including a large capacity non-volatile memory and at least one random access memory, said the access time of said device being matched to the access time of each random access memory. The semiconductor memory device is comprised of: a non-volatile memory FLASH having a first reading time; a random access memory DRAM having a second reading time which is more than 100 times shorter than the first reading time; a circuit that includes a control circuit connected to both the FLASH and the DRAM and enabled to control accesses to those FLASH and DRAM; and a plurality of I/O terminals connected to the circuit. As a result, FLASH data is transferred to the DRAM before the DRAM is accessed, thereby matching the access time between the FLASH and the DRAM. Data is written back from the DRAM to the FLASH as needed, thereby keeping data matched between the FLASH and the DRAM and storing the data.

摘要翻译： 一种包括大容量非易失性存储器和至少一个随机存取存储器的半导体器件，所述设备的访问时间与每个随机存取存储器的访问时间相匹配。 半导体存储器件包括：具有第一读取时间的非易失性存储器FLASH; 具有比第一读取时间短100倍的第二读取时间的随机存取存储器DRAM; 电路，其包括连接到FLASH和DRAM两者的控制电路，并且能够控制对那些FLASH和DRAM的访问; 以及连接到电路的多个I / O端子。 结果，在访问DRAM之前，将FLASH数据传送到DRAM，从而与FLASH和DRAM之间的访问时间相匹配。 数据根据需要从DRAM写回到FLASH，从而保持FLASH和DRAM之间的数据匹配并存储数据。

公开(公告)号：US20070211543A1

公开(公告)日：2007-09-13

申请号：US11797882

申请日：2007-05-08

申请人： Seiji Miura ,  Kazushige Ayukawa

发明人： Seiji Miura ,  Kazushige Ayukawa

IPC分类号： G11C7/00

CPC分类号： G06F12/0246 ,  G11C5/02 ,  G11C5/025 ,  G11C5/04 ,  G11C11/005 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/40607 ,  G11C11/412 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C29/70

摘要： A semiconductor device including a large capacity non-volatile memory and at least one random access memory, said the access time of said device being matched to the access time of each random access memory. The semiconductor memory device is comprised of: a non-volatile memory FLASH having a first reading time; a random access memory DRAM having a second reading time which is more than 100 times shorter than the first reading time; a circuit that includes a control circuit connected to both the FLASH and the DRAM and enabled to control accesses to those FLASH and DRAM; and a plurality of I/O terminals connected to the circuit. As a result, FLASH data is transferred to the DRAM before the DRAM is accessed, thereby matching the access time between the FLASH and the DRAM. Data is written back from the DRAM to the FLASH as needed, thereby keeping data matched between the FLASH and the DRAM and storing the data.

公开(公告)号：US20060221756A1

公开(公告)日：2006-10-05

申请号：US11439139

申请日：2006-05-24

申请人： Seiji Miura ,  Kazushige Ayukawa

发明人： Seiji Miura ,  Kazushige Ayukawa

IPC分类号： G11C8/00

CPC分类号： G06F12/0246 ,  G11C5/02 ,  G11C5/025 ,  G11C5/04 ,  G11C11/005 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/40607 ,  G11C11/412 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C29/70

摘要： A semiconductor device including a large capacity non-volatile memory and at least one random access memory, said the access time of said device being matched to the access time of each random access memory. The semiconductor memory device is comprised of: a non-volatile memory FLASH having a first reading time; a random access memory DRAM having a second reading time which is more than 100 times shorter than the first reading time; a circuit that includes a control circuit connected to both the FLASH and the DRAM and enabled to control accesses to those FLASH and DRAM; and a plurality of I/O terminals connected to the circuit. As a result, FLASH data is transferred to the DRAM before the DRAM is accessed, thereby matching the access time between the FLASH and the DRAM. Data is written back from the DRAM to the FLASH as needed, thereby keeping data matched between the FLASH and the DRAM and storing the data.

公开(公告)号：US07068562B2

公开(公告)日：2006-06-27

申请号：US11152526

申请日：2005-06-13

申请人： Seiji Miura ,  Kazushige Ayukawa

发明人： Seiji Miura ,  Kazushige Ayukawa

IPC分类号： G11C8/00

CPC分类号： G06F12/0246 ,  G11C5/02 ,  G11C5/025 ,  G11C5/04 ,  G11C11/005 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/40607 ,  G11C11/412 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C29/70

摘要： A semiconductor device including a large capacity non-volatile memory and at least one random access memory, said the access time of said device being matched to the access time of each random access memory. The semiconductor memory device is comprised of: a non-volatile memory FLASH having a first reading time; a random access memory DRAM having a second reading time which is more than 100 times shorter than the first reading time; a circuit that includes a control circuit connected to both the FLASH and the DRAM and enabled to control accesses to those FLASH and DRAM; and a plurality of I/O terminals connected to the circuit. As a result, FLASH data is transferred to the DRAM before the DRAM is accessed, thereby matching the access time between the FLASH and the DRAM. Data is written back from the DRAM to the FLASH as needed, thereby keeping data matched between the FLASH and the DRAM and storing the data.

公开(公告)号：US06945384B2

公开(公告)日：2005-09-20

申请号：US10876669

申请日：2004-06-28

申请人： Kouji Sakota ,  Masaaki Miura ,  Seiji Miura

发明人： Kouji Sakota ,  Masaaki Miura ,  Seiji Miura

IPC分类号： B65G47/14 ,  B65G15/58

CPC分类号： B65G47/1485 ,  B65G2201/02

摘要： A parts aligner is provided with an attraction means 8 orbitally movable in a specific orbit R, and also provided with a posture shift guide 11, a regulating piece 12 and a thickness sorting guide 13 along a specific circumference P corresponding to the specific orbit R in the order of the direction of orbital movement of the attraction means 8. With this structure, only regular parts shifted into a specific posture are guided to an alignment and feed guide 14 and irregular parts are stored in an irregular parts storing part 16.

摘要翻译： 零件对准器设置有可在特定轨道R中轨道移动的吸引装置8，并且还具有沿着与特定轨道R相对应的特定圆周P的姿态换档引导件11，调节片12和厚度分选引导件13 吸引装置8的轨道运动方向的顺序。 利用这种结构，只有移动到特定姿势的正常部件被引导到对准和进给引导件14，并且不规则部分被存储在不规则部分存储部分16中。