公开(公告)号：US07051295B2

公开(公告)日：2006-05-23

申请号：US10746759

申请日：2003-12-23

Applicant: Siva G. Narendra ,  Daniel S. Klowden ,  James W. Tschanz ,  Nitin Borkar ,  Vivek K. De

Inventor： Siva G. Narendra ,  Daniel S. Klowden ,  James W. Tschanz ,  Nitin Borkar ,  Vivek K. De

IPC: G06F17/50

CPC classification number: G06F17/5068

Abstract: An apparatus for and method of modifying an IC design layout of an integrated circuit, comprising: accessing an initial IC design layout, with the initial layout including a plurality of MOSFET devices having a common substrate; and removing a plurality of body contacts of the MOSFET devices to create a first modified IC design layout.

Abstract translation: 一种用于修改集成电路的IC设计布局的装置和方法，包括：访问初始IC设计布局，初始布局包括具有公共衬底的多个MOSFET器件; 以及去除所述MOSFET器件的多个体接触以产生第一修改的IC设计布局。

公开(公告)号：US07015720B2

公开(公告)日：2006-03-21

申请号：US10749928

申请日：2003-12-29

Applicant: Gerhard Schrom ,  Peter Hazucha ,  Jae-Hong Hahn ,  Vivek K. De

Inventor： Gerhard Schrom ,  Peter Hazucha ,  Jae-Hong Hahn ,  Vivek K. De

IPC: H03K19/0175

CPC classification number: H03K17/691 ,  H03K19/0013

Abstract: A circuit includes a first driver, a second driver, and a transformer coupled to the first and second driver. In operation, the first driver receives a first signal from a first input port, the second driver receives a time-delayed version of the first signal from a second input port, and the transformer provides provide an output signal to an output port. A method includes receiving a first input signal, receiving a second input signal, and then processing the first input signal and the second input signal. The second input signal is a time-delayed version of the first input signal and the processing of the first input signal and the second input signal generates a half-raised cosine signal.

Abstract translation: 电路包括第一驱动器，第二驱动器和耦合到第一和第二驱动器的变压器。 在操作中，第一驱动器从第一输入端口接收第一信号，第二驱动器从第二输入端口接收第一信号的时间延迟版本，并且变压器向输出端口提供输出信号。 一种方法包括接收第一输入信号，接收第二输入信号，然后处理第一输入信号和第二输入信号。 第二输入信号是第一输入信号的时间延迟版本，第一输入信号和第二输入信号的处理产生半升余弦信号。

公开(公告)号：US06992603B2

公开(公告)日：2006-01-31

申请号：US10813084

申请日：2004-03-31

Applicant: Maged M. Ghoneima ,  Peter Caputa ,  Muhammad M. Khellah ,  Ram Krishnamurthy ,  James W. Tschanz ,  Yiben Ye ,  Vivek K. De ,  Yehea I Ismail

Inventor： Maged M. Ghoneima ,  Peter Caputa ,  Muhammad M. Khellah ,  Ram Krishnamurthy ,  James W. Tschanz ,  Yiben Ye ,  Vivek K. De ,  Yehea I Ismail

IPC: H03M7/00

CPC classification number: G06F13/4072 ,  Y02D10/14 ,  Y02D10/151

Abstract: An interconnect architecture is provided to reduce power consumption. A first driver may drive signals on a first interconnect and a second driver may drive signals on a second interconnect. The first driver may be powered by a first voltage and the second driver may be powered by a second voltage different than the first voltage.

Abstract translation: 提供互连架构以降低功耗。 第一驱动器可以在第一互连上驱动信号，并且第二驱动器可以在第二互连上驱动信号。 第一驱动器可以由第一电压供电，并且第二驱动器可以由不同于第一电压的第二电压供电。

公开(公告)号：US06992339B2

公开(公告)日：2006-01-31

申请号：US10750572

申请日：2003-12-31

Applicant: Ali Keshavarzi ,  Stephen H. Tang ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Yibin Ye ,  Shih-Lien L. Lu ,  Vivek K. De

Inventor： Ali Keshavarzi ,  Stephen H. Tang ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Yibin Ye ,  Shih-Lien L. Lu ,  Vivek K. De

IPC: H01L27/10

CPC classification number: G11C11/404 ,  G11C2211/4016 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/108 ,  H01L29/7841

Abstract: Some embodiments provide a memory cell that includes a body region, a source region and a drain region. The body region is doped with charge carriers of a first type, the source region is disposed in the body region and doped with charge carriers of a second type, and the drain region is disposed in the body region and doped with charge carriers of the second type. The body region and the source region form a first junction, the body region and the drain region form a second junction, and a conductivity of the first junction from the body region to the source region in a case that the first junction is unbiased is substantially less than a conductivity of the second junction from the body region to the drain region in a case that the second junction is unbiased.

公开(公告)号：US06970018B2

公开(公告)日：2005-11-29

申请号：US10873243

申请日：2004-06-23

Applicant: Dejan Markovic ,  James W. Tschanz ,  Vivek K. De

Inventor： Dejan Markovic ,  James W. Tschanz ,  Vivek K. De

IPC: H03K3/012 ,  H03K3/037 ,  H03K3/356 ,  H03K19/094

CPC classification number: H03K3/356113 ,  H03K3/012 ,  H03K3/037 ,  H03K3/356156

Abstract: A cycle latch includes a control circuit which increases the pull-up rate of a storage node by conditionally discharging the feedback node in a cross-coupled inverter keeper structure. The cycle latch includes an NMOS transistor switch for transferring an input value to the storage node, and two more NMOS transistors connected in series for performing the function of the control circuit. By connecting the storage node to a pre-discharged feedback node and then driving the latch with a low-swing clock, improved performance in terms of delay times, energy consumption, and robustness is achieved.

Abstract translation: 循环锁存器包括控制电路，其通过在交叉耦合的逆变器保持器结构中有条件地排放反馈节点来增加存储节点的上拉率。 周期锁存器包括用于将输入值传送到存储节点的NMOS晶体管开关和串联连接的两个NMOS晶体管，用于执行控制电路的功能。 通过将存储节点连接到预放电反馈节点，然后用低摆频时钟驱动锁存器，实现延迟时间，能量消耗和鲁棒性方面的改进的性能。

公开(公告)号：US06906973B1

公开(公告)日：2005-06-14

申请号：US10746148

申请日：2003-12-24

Applicant: Dinesh Somasekhar ,  Yibin Ye ,  Muhammad M. Khellah ,  Fabrice Paillet ,  Stephen H. Tang ,  Ali Keshavarzi ,  Shih-Lien L. Lu ,  Vivek K. De

Inventor： Dinesh Somasekhar ,  Yibin Ye ,  Muhammad M. Khellah ,  Fabrice Paillet ,  Stephen H. Tang ,  Ali Keshavarzi ,  Shih-Lien L. Lu ,  Vivek K. De

IPC: G11C7/00 ,  G11C7/12

CPC classification number: G11C7/12

Abstract: Some embodiments provide pre-charge of a bit-line coupled to a memory cell to a reference voltage using a pre-charge device, discharge of the bit-line based on a value stored by the memory cell, injection during the discharge, of a first current into the bit-line using the pre-charge device, and injection, during the discharge, of a second current into a reference bit-line using a second pre-charge device. Also during the discharge, a difference is sensed between a voltage on the bit-line and a voltage on the reference bit-line.

Abstract translation: 一些实施例使用预充电器件将耦合到存储器单元的位线预充电至参考电压，基于存储器单元存储的值，放电期间的注入，放电期间的位线放电， 使用预充电器件进入位线的第一电流，以及在放电期间使用第二预充电器件将第二电流注入参考位线。 此外，在放电期间，在位线上的电压和参考位线上的电压之间感测到差异。

公开(公告)号：US06831871B2

公开(公告)日：2004-12-14

申请号：US10334456

申请日：2002-12-30

Applicant: Muhammad M. Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Vivek K. De

Inventor： Muhammad M. Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Vivek K. De

IPC: G11C700

CPC classification number: G11C7/12 ,  G11C2207/2281

Abstract: According to some embodiments, provided are a memory cell, a bit-line coupled to the memory cell, a pre-charge circuit coupled to the bit-line to pre-charge the bit-line, and a discharge device coupled to the bit-line to discharge the bit-line prior to a read of the memory cell.

公开(公告)号：US06825687B2

公开(公告)日：2004-11-30

申请号：US10230466

申请日：2002-08-29

Applicant: Ali Keshavarzi ,  Jaume A. Segura ,  Siva G. Narendra ,  Vivek K. De

Inventor： Ali Keshavarzi ,  Jaume A. Segura ,  Siva G. Narendra ,  Vivek K. De

IPC: H03K1716

CPC classification number: H03K19/0016 ,  H01L27/0251

Abstract: An apparatus and method for reducing leakage current of transistors used in an integrated circuit, which selectively switch a processor circuit in the integrated circuit to a standby state. A cooling device is included and selectively located in an area of the integrated circuit that is in close proximity to a transistor used to switch a processor circuit between active and standby states. The cooling device cools the transistor in order to improve both its leakage and active current states, thereby increasing efficiency of the transistor and reducing its leakage current.

Abstract translation: 一种用于降低在集成电路中使用的晶体管的泄漏电流的装置和方法，其选择性地将集成电路中的处理器电路切换到待机状态。 包括冷却装置并且选择性地位于集成电路的紧邻用于在主动状态和待机状态之间切换处理器电路的晶体管的区域中。 冷却装置冷却晶体管，以改善其泄漏和有功电流状态，从而提高晶体管的效率并减少其漏电流。

公开(公告)号：US06806739B2

公开(公告)日：2004-10-19

申请号：US10330544

申请日：2002-12-30

Applicant: Dejan Markovic ,  James W. Tschanz ,  Vivek K. De

Inventor： Dejan Markovic ,  James W. Tschanz ,  Vivek K. De

IPC: H03K19094

CPC classification number: H03K3/356113 ,  H03K3/012 ,  H03K3/037 ,  H03K3/356156

Abstract: A cycle latch includes a control circuit which increases the pull-up rate of a storage node by conditionally discharging the feedback node in a cross-coupled inverter keeper structure. The cycle latch includes an NMOS transistor switch for transferring an input value to the storage node, and two more NMOS transistors connected in series for performing the function of the control circuit. By connecting the storage node to a pre-discharged feedback node and then driving the latch with a low-swing clock, improved performance in terms of delay times, energy consumption, and robustness is achieved.

公开(公告)号：US06693332B2

公开(公告)日：2004-02-17

申请号：US10025047

申请日：2001-12-19

Applicant: Siva G. Narendra ,  Stephen H. Tang ,  Zachary Keer ,  Vivek K. De

Inventor： Siva G. Narendra ,  Stephen H. Tang ,  Zachary Keer ,  Vivek K. De

IPC: H01L2976

CPC classification number: G05F3/245 ,  Y10S257/919

Abstract: A current reference, which may be fabricated on a die, as part of an integrated circuit, or in various other forms, is disclosed. The current reference includes two current sources, both of which provide a substantially temperature stable output current, which may use a differencing circuit to provide a reference output current having a magnitude approximately equal to the difference between the magnitudes of the two substantially temperature stable output currents.

Abstract translation: 公开了可以在芯片上制造的作为集成电路的一部分或以各种其它形式的电流参考。 电流参考文献包括两个电流源，它们都提供基本上温度稳定的输出电流，其可以使用差分电路来提供参考输出电流，该参考输出电流的幅度近似等于两个基本上温度稳定的输出电流的幅度之差 。