公开(公告)号：US20150062134A1

公开(公告)日：2015-03-05

申请号：US14017742

申请日：2013-09-04

Applicant: Apple Inc.

Inventor： Peter F. Holland ,  Brijesh Tripathi ,  Hao Chen

IPC: G06T1/60 ,  G06T1/20

CPC classification number: G09G5/00 ,  G06F5/10 ,  G09G5/363 ,  H04N5/00 ,  H04N5/14 ,  H04N7/025 ,  H04N7/0884

Abstract: A graphics system may include one or more processing units for processing a current display frame, each processing unit including a plurality of parameter registers for storing parameter settings used in processing the current display frame. A parameter buffer in the graphics system may store frame packets, with each frame packet containing information corresponding to parameter settings to be used for at least one display frame. A control circuit coupled to the buffer and to the one or more processing units may retrieve a top frame packet from the parameter buffer and determine if the frame packet is an internal type, i.e., intended for internal registers in a respective processing unit or if it is an external type, i.e., intended for an external register elsewhere in the graphics system. Based on the type of frame packet, the control circuit may update one or more register values accordingly.

Abstract translation: 图形系统可以包括用于处理当前显示帧的一个或多个处理单元，每个处理单元包括用于存储用于处理当前显示帧的参数设置的多个参数寄存器。 图形系统中的参数缓冲器可以存储帧分组，每个帧分组包含对应于要用于至少一个显示帧的参数设置的信息。 耦合到缓冲器和一个或多个处理单元的控制电路可以从参数缓冲器检索顶部帧分组，并且确定帧分组是否是内部类型，即针对相应处理单元中的内部寄存器，或者如果它 是一种外部类型，即用于图形系统中其他地方的外部寄存器。 基于帧分组的类型，控制电路可以相应地更新一个或多个寄存器值。

公开(公告)号：US20140292787A1

公开(公告)日：2014-10-02

申请号：US13850548

申请日：2013-03-26

Applicant: APPLE INC.

Inventor： Brijesh Tripathi ,  Peter F. Holland ,  Albert C. Kuo

IPC: G09G5/395

CPC classification number: G09G5/395 ,  G06F3/14 ,  G09G5/001 ,  G09G5/393 ,  G09G2330/02 ,  G09G2330/021 ,  G09G2340/02 ,  G09G2360/121

Abstract: In an embodiment, a display pipe is configured to composite one or more frames of images and/or video sequences to generate output frames for display. Additionally, the display pipe may be configured to compress an output frame and write the compressed frame to memory responsive to detecting static content in the output frames is detected. The display pipe may also be configured to read the compressed frame from memory for display instead of reading the frames for compositing and display. In some embodiments, the display pipe may include an idle screen detect circuit configured to monitor the operation of the display pipe and/or the output frames to detect the static content.

Abstract translation: 在一个实施例中，显示管被配置为组合一个或多个图像帧和/或视频序列以产生用于显示的输出帧。 此外，显示管可以被配置为压缩输出帧并且响应于检测到输出帧中的静态内容而将压缩帧写入存储器。 显示管还可以被配置为从存储器读取压缩帧用于显示，而不是读取用于合成和显示的帧。 在一些实施例中，显示管道可以包括被配置为监视显示管道和/或输出框架的操作以检测静态内容的空闲屏幕检测电路。

公开(公告)号：US20140253570A1

公开(公告)日：2014-09-11

申请号：US13788209

申请日：2013-03-07

Applicant: APPLE INC.

Inventor： Brijesh Tripathi ,  Peter F. Holland ,  Timothy J. Millet

IPC: G06T1/60

CPC classification number: G06T1/60 ,  G09G5/006 ,  G09G2340/0442 ,  G09G2340/0492 ,  G09G2360/125 ,  G09G2370/10

Abstract: In an embodiment, a system includes hardware optimized for communication to a network display. The hardware may include a display pipe unit that is configured to composite one or more static images and one or more frames from video sequences to form frames for display by a network display. The display pipe unit may include a writeback unit configured to write the composite frames back to memory, from which the frames can be optionally encoded using video encoder hardware and packetized for transmission over a network to a network display. In an embodiment, the display pipe unit may be configured to issue interrupts to the video encoder during generation of a frame, to overlap encoding and frame generation.

Abstract translation: 在一个实施例中，系统包括针对与网络显示器进行通信而优化的硬件。 硬件可以包括显示管单元，其被配置为将来自视频序列的一个或多个静态图像和一个或多个帧组合以形成用于由网络显示器显示的帧。 显示管单元可以包括写回单元，其被配置为将复合帧写回到存储器，可以使用视频编码器硬件来选择性地对帧进行编码，并将其分组化以便通过网络传输到网络显示器。 在一个实施例中，显示管单元可以被配置为在帧的生成期间向视频编码器发出中断，以重叠编码和帧生成。

公开(公告)号：US12271250B2

公开(公告)日：2025-04-08

申请号：US17949834

申请日：2022-09-21

Applicant: Apple Inc.

Inventor： Ramana V. Rachakonda ,  Peter F. Holland ,  Rohit K. Gupta ,  Brad W. Simeral

IPC: G06F1/3234 ,  G06F1/18 ,  G06F1/3218 ,  G09G3/20

Abstract: An electronic device may include a display panel. When content of an image frame is expected to consume relatively higher amounts of power, a controller of the electronic device may operate a switch to change a power supply of the display panel to be a power management integrated circuit of the electronic device. However, when content of an image frame is expected to consume relatively less amounts of power, the controller may operate the switch to change the power supply of the display panel to be a power supply of an electronic display, such as a power supply used to power driver circuitry of the electronic display.

公开(公告)号：US12141016B2

公开(公告)日：2024-11-12

申请号：US18476547

申请日：2023-09-28

Applicant: Apple Inc.

Inventor： Ramana V. Rachakonda ,  Rohit K. Gupta ,  Brad W. Simeral ,  Peter F. Holland

IPC: G06F1/32 ,  G06F1/3228 ,  G06F1/3287 ,  H04B17/318

Abstract: In an embodiment, a system may include one or more processors forming central processing units (CPUs) in the system, a display controller configured to display frames on a display device, a memory controller configured to control a memory, and a power management circuit. The power management circuit may be configured to establish one of a plurality of power states in the system. In a first power state, the display controller and the memory controller are powered on while the CPUs are powered off. The display controller may be configured to read a plurality of prerendered frames from the memory and display the plurality of prerendered frames at times specified for each of the plurality of prerendered frames.

公开(公告)号：US20240013692A1

公开(公告)日：2024-01-11

申请号：US18212710

申请日：2023-06-21

Applicant: Apple Inc.

Inventor： Jie Won Ryu ,  Ardra Singh ,  Arthur L. Spence ,  Christopher P. Tann ,  Chun Lu ,  Daniel J. Drusch ,  Hyunwoo Nho ,  Jongyup Lim ,  Kingsuk Brahma ,  Marc J. DeVincentis ,  Mohammad Ali Jangda ,  Paolo Sacchetto ,  Peter F. Holland ,  Shawn P. Hurley ,  Wei H. Yao ,  Yue Jack Chu ,  Zhe Hua

IPC: G09G3/20

CPC classification number: G09G3/20 ,  G09G2330/021 ,  G09G2360/16 ,  G09G2320/103

Abstract: To reduce overall power consumption for an electronic display power management integrated circuit (PMIC), one of multiple electric power converters and/or electric power regulators may be selected based on an electrical load (e.g., due to the total brightness of the content displayed) on the electronic display at a given moment. In some embodiments, the PMIC may include a less efficient heavy load converter designed with high-current handling capability and a more efficient light load (e.g., low current) converter with lower current handling capability. A controller may dynamically select between the converters depending on a present load or an expected load on the electronic display.

公开(公告)号：US11868162B2

公开(公告)日：2024-01-09

申请号：US18083193

申请日：2022-12-16

Applicant: Apple Inc.

Inventor： Assaf Menachem ,  Peter F. Holland ,  Yung-Chin Chen

IPC: G06F3/14 ,  G09G5/12

CPC classification number: G06F3/1431 ,  G09G5/12 ,  G09G2310/08 ,  G09G2360/04

Abstract: A method may include receiving, via a processor, a frame of image data, such that the frame of image data may include an active portion and an idle portion. The active portion may include data for presenting one or more images via a first display of a first electronic device. The method may also include receiving a signal from a second electronic device during the idle portion of the frame of image data, such that the second electronic device is separate from the first display. The method may then involve initiating processing of the frame of image data in response to the signal being received from the second electronic device.

公开(公告)号：US11385982B2

公开(公告)日：2022-07-12

申请号：US16401364

申请日：2019-05-02

Applicant: Apple Inc.

Inventor： Peter F. Holland ,  Hari Ganesh R. Thirunageswaram

IPC: G06F13/40 ,  H03K19/0175 ,  H03K3/3565 ,  G06F11/30

Abstract: In an embodiment, an integrated circuit includes one or more GPIO pins coupled to a GPIO block in the integrated circuit. At least a first GPIO pin may include corresponding logic circuitry that may be programmed to apply one or more requirements to changes of the digital value received on the first GPIO pin before the change is forwarded to a destination within the integrated circuit. That is, if the requirements are not met for a given change, the logic circuitry may suppress the given change so that it is not provided to other circuits internal to the integrated circuit (e.g. the destination circuit that receives communication via the GPIO pins). The one or more requirements may be a form of hysteresis, for example.

公开(公告)号：US20220083304A1

公开(公告)日：2022-03-17

申请号：US17148512

申请日：2021-01-13

Applicant: Apple Inc.

Inventor： Assaf Menachem ,  Peter F. Holland ,  Yung-Chin Chen

IPC: G06F3/14 ,  G09G5/12

Abstract: A method may include receiving, via a processor, a frame of image data, such that the frame of image data may include an active portion and an idle portion. The active portion may include data for presenting one or more images via a first display of a first electronic device. The method may also include receiving a signal from a second electronic device during the idle portion of the frame of image data, such that the second electronic device is separate from the first display. The method may then involve initiating processing of the frame of image data in response to the signal being received from the second electronic device.

公开(公告)号：US20220075440A1

公开(公告)日：2022-03-10

申请号：US17015288

申请日：2020-09-09

Applicant: Apple Inc.

Inventor： Ramana V. Rachakonda ,  Rohit K. Gupta ,  Brad W. Simeral ,  Peter F. Holland

IPC: G06F1/3287 ,  G06F1/3228

Abstract: In an embodiment, a system may include one or more processors forming central processing units (CPUs) in the system, a display controller configured to display frames on a display device, a memory controller configured to control a memory, and a power management circuit. The power management circuit may be configured to establish one of a plurality of power states in the system. In a first power state, the display controller and the memory controller are powered on while the CPUs are powered off. The display controller may be configured to read a plurality of prerendered frames from the memory and display the plurality of prerendered frames at times specified for each of the plurality of prerendered frames.