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    SEMICONDUCTOR MEMORY HAVING ELECTRICALLY FLOATING BODY TRANSISTOR
    94.
    发明申请
    SEMICONDUCTOR MEMORY HAVING ELECTRICALLY FLOATING BODY TRANSISTOR 有权
    具有电浮动体晶体管的半导体存储器

    公开(公告)号：US20120012915A1

    公开(公告)日：2012-01-19

    申请号：US13244839

    申请日：2011-09-26

    申请人： Yuniarto Widjaja ,  Zvi Or-Bach

    发明人： Yuniarto Widjaja ,  Zvi Or-Bach

    IPC分类号： H01L29/788

    CPC分类号： G11C11/404 ,  G11C11/56 ,  G11C11/565 ,  G11C14/0018 ,  G11C14/0045 ,  G11C16/0416 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/11521 ,  H01L27/24 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7841 ,  H01L29/7881

    摘要： A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; a gate positioned between said first and second regions; and a back-bias region configured to inject charge into or extract charge out of said floating body region to maintain said state of the memory cell. Application of back bias to the back bias region offsets charge leakage out of the floating body and performs a holding operation on the cell. The cell may be a multi-level cell. Arrays of memory cells are disclosed for making a memory device.

    摘要翻译： 半导体存储单元包括被配置为被充电到指示存储单元的状态的电平的浮动体区域; 与所述浮体区域电接触的第一区域; 与所述浮体区域电接触并与所述第一区域间隔开的第二区域; 位于所述第一和第二区域之间的门; 以及背偏置区域，被配置为将电荷注入或从所述浮体区域中提取电荷以维持存储单元的所述状态。 将背偏置施加到背偏置区域将电荷泄漏偏离浮体，并对电池执行保持操作。 单元可以是多级单元。 公开了用于制造存储器件的存储器单元阵列。

    METHOD OF OPERATING SEMICONDUCTOR MEMORY DEVICE WITH FLOATING BODY TRANSISTOR USING SILICON CONTROLLED RECTIFIER PRINCIPLE
    98.
    发明申请
    METHOD OF OPERATING SEMICONDUCTOR MEMORY DEVICE WITH FLOATING BODY TRANSISTOR USING SILICON CONTROLLED RECTIFIER PRINCIPLE 有权

    公开(公告)号：US20100034041A1

    公开(公告)日：2010-02-11

    申请号：US12533661

    申请日：2009-07-31

    申请人： Yuniarto Widjaja

    发明人： Yuniarto Widjaja

    IPC分类号： G11C7/00 ,  G11C7/22 ,  G11C11/34

    CPC分类号： H01L27/10802 ,  G11C11/404 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/4096 ,  G11C2211/4016 ,  H01L29/7841

    摘要： Methods of operating semiconductor memory devices with floating body transistors, using a silicon controlled rectifier principle are provided, as are semiconductor memory devices for performing such operations. A method of maintaining the data state of a semiconductor dynamic random access memory cell is provided, wherein the memory cell comprises a substrate being made of a material having a first conductivity type selected from p-type conductivity type and n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type; a second region having the second conductivity type, the second region being spaced apart from the first region; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; and a gate positioned between the first and second regions and adjacent the body region. The memory cell is configured to store a first data state which corresponds to a first charge in the body region in a first configuration, and a second data state which corresponds to a second charge in the body region in a second configuration. The method includes: providing the memory cell storing one of the first and second data states; and applying a positive voltage to a substrate terminal connected to the substrate beneath the buried layer, wherein when the body region is in the first state, the body region turns on a silicon controlled rectifier device of the cell and current flows through the device to maintain configuration of the memory cell in the first memory state, and wherein when the memory cell is in the second state, the body region does not turn on the silicon controlled rectifier device, current does not flow, and a blocking operation results, causing the body to maintain the second memory state.

    SEMICONDUCTOR MEMORY HAVING BOTH VOLATILE AND NON-VOLATILE FUNCTIONALITY AND METHOD OF OPERATING
    99.
    发明申请
    SEMICONDUCTOR MEMORY HAVING BOTH VOLATILE AND NON-VOLATILE FUNCTIONALITY AND METHOD OF OPERATING 有权
    具有两种挥发性和非挥发性功能的半导体存储器及其操作方法

    公开(公告)号：US20090108322A1

    公开(公告)日：2009-04-30

    申请号：US12256868

    申请日：2008-10-23

    申请人： Yuniarto Widjaja

    发明人： Yuniarto Widjaja

    IPC分类号： H01L29/00

    CPC分类号： G11C14/0018 ,  G11C11/404 ,  G11C16/0408 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/225 ,  G11C2211/4016 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/84 ,  H01L27/105 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10826 ,  H01L27/10879 ,  H01L27/10897 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7841 ,  H01L29/785 ,  H01L29/7885 ,  H01L29/7887 ,  H01L29/792 ,  H01L29/7923

    摘要： Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor memory cell includes a fin structure extending from a substrate, the fin structure including a floating substrate region having a first conductivity type configured to store data as volatile memory; first and second regions interfacing with the floating substrate region, each of the first and second regions having a second conductivity type; first and second floating gates or trapping layers positioned adjacent opposite sides of the floating substrate region; a first insulating layer positioned between the floating substrate region and the floating gates or trapping layers, the floating gates or trapping layers being configured to receive transfer of data stored by the volatile memory and store the data as nonvolatile memory in the floating gates or trapping layers upon interruption of power to the memory cell; a control gate wrapped around the floating gates or trapping layers and the floating substrate region; and a second insulating layer positioned between the floating gates or trapping layers and the control gate; the substrate including an isolation layer that isolates the floating substrate region from a portion of the substrate below the isolation layer.

    摘要翻译： 具有易失性和非易失性模式和操作方法的半导体存储器。 半导体存储单元包括从衬底延伸的翅片结构，所述鳍结构包括具有第一导电类型的浮置衬底区域，其被配置为将数据存储为易失性存储器; 第一和第二区域与浮动衬底区域相接合，第一和第二区域中的每一个具有第二导电类型; 位于浮置衬底区域的相对侧的第一和第二浮栅或俘获层; 位于所述浮置衬底区域和所述浮置栅极或俘获层之间的第一绝缘层，所述浮置栅极或俘获层被配置为接收由所述易失性存储器存储的数据的传送，并将所述数据作为非易失性存储器存储在所述浮置栅极或俘获层中 在中断存储器单元的电源时; 围绕浮动栅极或捕获层和浮置衬底区域的控制栅极; 以及位于所述浮置栅极或俘获层之间的第二绝缘层和所述控制栅极; 所述衬底包括将所述浮置衬底区域与所述隔离层下方的所述衬底的一部分隔离的隔离层。