公开(公告)号：US11831312B2

公开(公告)日：2023-11-28

申请号：US17678962

申请日：2022-02-23

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Bahattin Kilic ,  Jie-Hua Zhao ,  Kunzhong Hu ,  Suk-Kyu Ryu

IPC: H03K19/1776 ,  G06F15/78 ,  H01L23/31 ,  H05K1/02

CPC classification number: H03K19/1776 ,  G06F15/7807 ,  H01L23/3114 ,  H05K1/0298

Abstract: Multi-chip systems and structures for modular scaling are described. In some embodiments an interfacing bar is utilized to couple adjacent chips. For example, a communication bar may utilized to coupled logic chips, and memory bar may be utilized to couple multiple memory chips to a logic chip.

公开(公告)号：US20230335494A1

公开(公告)日：2023-10-19

申请号：US18339102

申请日：2023-06-21

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Zhitao Cao ,  Kunzhong Hu ,  Jun Zhai

IPC: H01L23/528 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H05K1/11 ,  H05K1/18

CPC classification number: H01L23/5286 ,  H01L23/49816 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L25/0652 ,  H05K1/111 ,  H05K1/181 ,  H01L24/16

Abstract: Electronic package structures and systems are described in which a 3D interconnect structure is integrated into a package redistribution layer and/or chiplet for power and signal delivery to a die. Such structures may significantly improve input output (TO) density and routing quality for signals, while keeping power delivery feasible.

公开(公告)号：US11735567B2

公开(公告)日：2023-08-22

申请号：US17484188

申请日：2021-09-24

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Jun Zhai ,  Kwan-Yu Lai ,  Kunzhong Hu ,  Vidhya Ramachandran

IPC: H01L25/065 ,  H01L21/56 ,  H01L21/768 ,  H01L21/78 ,  H01L21/66 ,  H01L23/48 ,  H01L23/60 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76897 ,  H01L21/78 ,  H01L22/32 ,  H01L23/481 ,  H01L23/60 ,  H01L24/96 ,  H01L25/50 ,  H01L2224/95001 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/30205

Abstract: Stitched die packaging techniques and structures are described in which reconstituted chips are formed using wafer reconstitution and die-stitching techniques. In an embodiment, a chip includes a reconstituted chip-level back end of the line (BEOL) build-up structure to connect a die set embedded in an inorganic gap fill material.

公开(公告)号：US20230245988A1

公开(公告)日：2023-08-03

申请号：US18058006

申请日：2022-11-22

Applicant: Apple Inc.

Inventor： Kwan-Yu Lai ,  Kunzhong Hu ,  Jun Zhai ,  Young Doo Jeon

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L24/73 ,  H01L24/13 ,  H01L24/20 ,  H01L24/19 ,  H01L24/14 ,  H01L2224/73101 ,  H01L2224/2101 ,  H01L2224/2105 ,  H01L2224/211 ,  H01L2224/214 ,  H01L2224/19 ,  H01L2224/11002 ,  H01L2224/11916 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/1184 ,  H01L2224/14131 ,  H01L2224/14133 ,  H01L2224/13005 ,  H01L2224/13014 ,  H01L2224/13018 ,  H01L2224/13075 ,  H01L2224/13541 ,  H01L2224/13552 ,  H01L2224/13575 ,  H01L2924/35121

Abstract: Die reconstitution methods and dies with reconstituted contact bumps are described. In an embodiment, a die reconstitution method includes reconstituting a plurality of dies including first contact bumps of a first type, partially removing the first contact bumps, and forming second contact bumps of a second type on top of the partially removed first contact bumps, where the second type is different than the first type.

公开(公告)号：US20220285273A1

公开(公告)日：2022-09-08

申请号：US17699563

申请日：2022-03-21

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Zhitao Cao ,  Kunzhong Hu ,  Jun Zhai

IPC: H01L23/528 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H05K1/11 ,  H05K1/18

Abstract: Electronic package structures and systems are described in which a 3D interconnect structure is integrated into a package redistribution layer and/or chiplet for power and signal delivery to a die. Such structures may significantly improve input output (IO) density and routing quality for signals, while keeping power delivery feasible.

公开(公告)号：US20210305227A1

公开(公告)日：2021-09-30

申请号：US17013279

申请日：2020-09-04

Applicant: Apple Inc.

Inventor： Wei Chen ,  Jie-Hua Zhao ,  Jun Zhai ,  Po-Hao Chang ,  Hsien-Che Lin ,  Ying-Chieh Ke ,  Kunzhong Hu

IPC: H01L25/18 ,  H01L23/24

Abstract: Multiple chip module (MCM) structures are described. In an embodiment, a module includes a first and second components on the top side of a module substrate, a stiffener structure mounted on the top side of the module substrate, and a lid mounted on the stiffener structure and covering the first component and the second component. The stiffener is joined to the lid within a trench formed in a roof of the lid.

公开(公告)号：US20210242170A1

公开(公告)日：2021-08-05

申请号：US16783132

申请日：2020-02-05

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Zhitao Cao ,  Kunzhong Hu ,  Jun Zhai

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/498 ,  H05K1/11 ,  H05K1/18

Abstract: Electronic package structures and systems are described in which a 3D interconnect structure is integrated into a package redistribution layer and/or chiplet for power and signal delivery to a die. Such structures may significantly improve input output (TO) density and routing quality for signals, while keeping power delivery feasible.

公开(公告)号：US11056373B2

公开(公告)日：2021-07-06

申请号：US14918189

申请日：2015-10-20

Applicant: Apple Inc.

Inventor： Jun Zhai ,  Kwan-Yu Lai ,  Kunzhong Hu

IPC: H01L23/538 ,  H01L21/56 ,  H01L25/065 ,  H01L21/683 ,  H01L23/00 ,  H01L25/03 ,  H01L25/00 ,  H01L23/31 ,  H01L23/498

Abstract: Semiconductor packages and fan out die stacking processes are described. In an embodiment, a package includes a first level die and a row of conductive pillars protruding from a front side of the first level die. A second level active die is attached to the front side of the first level die, and a redistribution layer (RDL) is formed on an in electrical contact with the row of conductive pillars and a front side of the second level active die.

公开(公告)号：US10943869B2

公开(公告)日：2021-03-09

申请号：US15817054

申请日：2017-11-17

Applicant: Apple Inc.

Inventor： Jun Zhai ,  Chonghua Zhong ,  Kunzhong Hu

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/683 ,  H01L23/498 ,  H01L25/00 ,  H01L23/16 ,  H01L23/00 ,  H01L25/10 ,  H01L25/065 ,  H01L25/18 ,  H01L23/31

Abstract: Multiple component package structures are described in which an interposer chiplet is integrated to provide fine routing between components. In an embodiment, the interposer chiplet and a plurality of conductive vias are encapsulated in an encapsulation layer. A first plurality of terminals of the first and second components may be in electrical connection with the plurality of conductive pillars and a second plurality of terminals of first and second components may be in electrical connection with the interposer chiplet.

公开(公告)号：US10685948B1

公开(公告)日：2020-06-16

申请号：US16204679

申请日：2018-11-29

Applicant: Apple Inc.

Inventor： Chonghua Zhong ,  Jun Zhai ,  Kunzhong Hu

IPC: H01L23/52 ,  H01L25/18 ,  H01L23/538 ,  H01L23/00

Abstract: Double side mounted package structures and memory modules incorporating such double side mounted package structures are described in which memory packages are mounted on both sides of a module substrate. A routing substrate is mounted to a bottom side of the module substrate to provide general purpose in/out routing and power routing, while signal routing from the logic die to double side mounted memory packages is provided in the module routing. In an embodiment, module substrate is a coreless module substrate and may be thinner than the routing substrate.