公开(公告)号：US07985697B2

公开(公告)日：2011-07-26

申请号：US12208512

申请日：2008-09-11

申请人： Jong Tae Moon ,  Yong Sung Eom ,  Min Ji Lee ,  Hyun Kyu Yu

发明人： Jong Tae Moon ,  Yong Sung Eom ,  Min Ji Lee ,  Hyun Kyu Yu

IPC分类号： H01L21/31

CPC分类号： H01L23/10 ,  B81B7/007 ,  B81C2203/0118 ,  H01L24/45 ,  H01L24/48 ,  H01L24/94 ,  H01L2224/16145 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/1461 ,  H01L2924/16235 ,  H01L2924/00 ,  H01L2924/2076 ,  H01L2224/05599

摘要： Provided are a wafer level package in which a communication line can be readily formed between an internal device and the outside of the package, and a method of fabricating the wafer level package. The wafer level package includes a first substrate having a cavity in which a first internal device is disposed, an Input/Output (I/O) pad formed on the first substrate and electrically connected with the first internal device, a second substrate disposed over the first substrate and from which a part corresponding to the I/O pad is removed, and a solder bonding the first and second substrates. According to the wafer level package and the method of fabricating the same, upper and lower substrates are sawed to different cutting widths, or a hole is formed in the upper substrate, such that a communication line of an internal device can be readily formed without a via process which penetrates a substrate. Therefore, in comparison with a conventional wafer level package fabricated using the via process, it is possible to simplify a fabrication process and reduce production cost.

摘要翻译： 提供了一种晶片级封装，其中可以容易地在内部器件和封装外部之间形成通信线，以及制造晶片级封装的方法。 晶片级封装包括具有第一内部器件的空腔的第一衬底，形成在第一衬底上并与第一内部器件电连接的输入/输出（I / O）焊盘，设置在第一衬底上的第二衬底 第一衬底并且从其中除去对应于I / O焊盘的部分，以及焊接第一和第二衬底的焊料。 根据晶片级封装及其制造方法，上下基板被切割成不同的切割宽度，或者在上基板上形成孔，使得可以容易地形成内部装置的连通线，而不需要 穿过基底的过程。 因此，与使用通孔工艺制造的常规晶片级封装相比，可以简化制造工艺并降低生产成本。

公开(公告)号：US20110150138A1

公开(公告)日：2011-06-23

申请号：US12970899

申请日：2010-12-16

申请人： Jung Woo PARK ,  Young Jae Lee ,  Hyun Kyu Yu ,  Byung Hun Min ,  Seong Do Kim ,  Hoai Nam Nguyen ,  Sang Gug Lee

发明人： Jung Woo PARK ,  Young Jae Lee ,  Hyun Kyu Yu ,  Byung Hun Min ,  Seong Do Kim ,  Hoai Nam Nguyen ,  Sang Gug Lee

IPC分类号： H03K9/00

CPC分类号： H04L25/08 ,  H03D7/1441 ,  H03D7/1458 ,  H03H19/004

摘要： A direct conversion receiver includes: a high linearity mixer device including a sampler unit charge-sampling an input current according to a sampling frequency, and a buffer unit receiving an output signal from the sampler unit while having a low input impedance, amplifying the received signal, and outputting a current signal; and a filter device decimating an output signal from the mixer device and FIR-filtering the decimated signal.

摘要翻译： 直接转换接收机包括：高线性混频器装置，包括：采样单元，根据采样频率对输入电流进行采样;以及缓冲单元，其具有低输入阻抗，从采样器单元接收输出信号，放大接收信号 ，并输出电流信号; 以及滤波器装置对来自混频器装置的输出信号进行抽取，并对抽取的信号进行FIR滤波。

公开(公告)号：US20110148490A1

公开(公告)日：2011-06-23

申请号：US12956498

申请日：2010-11-30

申请人： Ja Yol Lee ,  Seon Ho Han ,  Mi Jeong Park ,  Jang Hong Choi ,  Seong Do Kim ,  Hyun Kyu Yu

发明人： Ja Yol Lee ,  Seon Ho Han ,  Mi Jeong Park ,  Jang Hong Choi ,  Seong Do Kim ,  Hyun Kyu Yu

IPC分类号： H03L7/08 ,  H03M1/50

CPC分类号： H03L7/095 ,  G04F10/005 ,  H03L7/085 ,  H03L7/103 ,  H03L2207/50

摘要： An all digital phase-locked loop (ADPLL) includes: a phase counter accumulating a frequency setting word value and the phase of a digitally controlled oscillator (DCO) clock and detecting a fine phase difference between a reference clock and a retimed clock; a phase detector detecting a digital phase error value compensating for a phase difference between the frequency setting word value and the DCO clock according to the fine phase difference to detect a digital phase error value; a digital loop filter filtering the digital phase error value and controlling PLL operational characteristics; a lock detector generating a lock indication signal according an output of the digital loop filter; a digitally controlled oscillator varying the frequency of the DCO clock according to the output from the digital loop filter; and a retimed clock generator generating the retimed clock by retiming the DCO clock at a low frequency.

摘要翻译： 全数字锁相环（ADPLL）包括：相位计数器累积频率设定字值和数字控制振荡器（DCO）时钟的相位，并检测参考时钟和重新定时钟之间的精细相位差; 相位检测器，根据所述精细相位差检测补偿所述频率设定字值与所述DCO时钟之间的相位差的数字相位误差值，以检测数字相位误差值; 数字环路滤波器滤除数字相位误差值并控制PLL的操作特性; 锁定检测器，根据数字环路滤波器的输出产生锁定指示信号; 数字控制振荡器根据数字环路滤波器的输出来改变DCO时钟的频率; 以及重新计时的时钟发生器，通过以低频再定时DCO时钟产生重定时钟。

公开(公告)号：US07892880B2

公开(公告)日：2011-02-22

申请号：US12724667

申请日：2010-03-16

申请人： Eun Soo Nam ,  Myoung Sook Oh ,  Ho Young Kim ,  Young Jun Chong ,  Hyun Kyu Yu

发明人： Eun Soo Nam ,  Myoung Sook Oh ,  Ho Young Kim ,  Young Jun Chong ,  Hyun Kyu Yu

IPC分类号： H01L21/00

CPC分类号： H01L27/14643 ,  G01S7/4863 ,  G01S17/89 ,  H01L27/14681 ,  H04N5/369

摘要： A method of manufacturing a photo-detector array device integrated with a read-out integrated circuit (ROIC) monolithically integrated for a laser-radar image signal. A detector array device, a photodiode and control devices for selecting and outputting a laser-radar image signal are simultaneously formed on an InP substrate. In addition, after the photodiode and the control devices are simultaneously formed on the InP substrate, the photodiode and the control devices are electrically separated from each other using a polyamide, whereby a PN junction surface of the photodiode is buried to reduce surface leakage current and improve electrical reliability, and the structure of the control devices can be simplified to improve image signal reception characteristics.

摘要翻译： 一种制造与用于激光雷达图像信号单片集成的读出集成电路（ROIC）集成的光电检测器阵列装置的方法。 在InP衬底上同时形成用于选择和输出激光雷达图像信号的检测器阵列器件，光电二极管和控制器件。 此外，在InP衬底上同时形成光电二极管和控制装置之后，使用聚酰胺将光电二极管和控制装置彼此电分离，由此埋入光电二极管的PN结表面以减小表面泄漏电流， 提高电气可靠性，可以简化控制装置的结构，提高图像信号接收特性。

公开(公告)号：US20100322361A1

公开(公告)日：2010-12-23

申请号：US12818510

申请日：2010-06-18

申请人： Seon-Ho HAN ,  Hyun Kyu Yu

发明人： Seon-Ho HAN ,  Hyun Kyu Yu

IPC分类号： H04L27/08

CPC分类号： H04B1/0025 ,  H04B1/001

摘要： In a digital receiver, a noise attenuation and signal magnitude mapping variable amplifying unit includes a filter and an amplifier, amplifies and band-bass filters an analog signal and attenuating white noise and an interference signal other than a band signal. An ADC performs sub sampling on a carrier frequency of a desired signal and performs oversampling on the band of the desired signal by using a sampling frequency to convert the analog signal which has passed through the noise attenuation and signal magnitude mapping variable amplifying unit into a digital signal of a direct conversion frequency band or an intermediate frequency band. The ADC has a dynamic range for processing both the desired signal and an undesired signal adjacent to the desired signal. A digital signal processing unit converts a signal frequency of the digital signal or digital-filters an undesired signal within the digital signal and processes the digital signal by digitally adjusting a gain.

摘要翻译： 在数字接收机中，噪声衰减和信号幅度映射可变放大单元包括滤波器和放大器，对模拟信号进行放大和频带滤波，并衰减白噪声和除频带信号之外的干扰信号。 ADC对期望信号的载波频率进行子采样，并通过使用采样频率对已经通过噪声衰减和信号幅度可变放大单元的模拟信号进行数字化处理，对期望信号的频带进行过采样， 直接转换频带或中频带的信号。 ADC具有用于处理期望信号和与期望信号相邻的不期望信号的动态范围。 数字信号处理单元转换数字信号的信号频率或数字滤波数字信号内的不需要的信号，并通过数字调节增益来处理数字信号。

公开(公告)号：US20100090761A1

公开(公告)日：2010-04-15

申请号：US12511323

申请日：2009-07-29

申请人： Sang Jin Byun ,  Jae Hoon Shim ,  Hyun Kyu Yu

发明人： Sang Jin Byun ,  Jae Hoon Shim ,  Hyun Kyu Yu

IPC分类号： H03D3/00

CPC分类号： H04L27/233 ,  H04L27/2338

摘要： A PSK demodulator using a time-to-digital converter includes: a filter unit that performs band pass filtering on a PSK signal; an amplitude limiting unit that limits the amplitude of an output signal of the filter unit; a clock signal generating unit that generates a clock signal; and a time-to-digital converter that samples the phase of an output signal of the amplitude limiting unit according to the clock signal and outputs a digital signal having a value corresponding to the phase of the PSK signal. Power consumption can be reduced and a circuit implementation can be simplified.

摘要翻译： 使用时间 - 数字转换器的PSK解调器包括：对PSK信号执行带通滤波的滤波器单元; 幅度限制单元，限制滤波器单元的输出信号的幅度; 时钟信号生成单元，生成时钟信号; 以及时间 - 数字转换器，其根据时钟信号对幅度限制单元的输出信号的相位进行采样，并输出具有与PSK信号的相位对应的值的数字信号。 可以降低功耗并简化电路实现。

公开(公告)号：US07532001B2

公开(公告)日：2009-05-12

申请号：US11447747

申请日：2006-06-06

申请人： Young Jae Lee ,  Hyun Kyu Yu

发明人： Young Jae Lee ,  Hyun Kyu Yu

IPC分类号： G01R33/00

CPC分类号： H03B5/1228 ,  H03B5/1212 ,  H03B5/124 ,  H03B5/1296

摘要： Provided is a Q-boosting circuit for improving a Q factor in a radio frequency (RF) integrated circuit of a semiconductor device using a transformer instead of an inductor. The Q-boosting circuit couples a negative resistance circuit to a pair of terminals of a transformer to reduce a resistance component of the transformer, thereby increasing a mutual inductance component. Therefore, it is possible to obtain a more improved Q factor than a conventional Q factor through adjustment of an inductance and a resistance component, and to obtain the Q factor having a wide range from several tens to several hundreds according to a frequency range.

摘要翻译： 提供了一种用于使用变压器代替电感器来改善半导体器件的射频（RF）集成电路中的Q因子的Q升压电路。 Q升压电路将负电阻电路耦合到变压器的一对端子，以减小变压器的电阻分量，从而增加互感元件。 因此，可以通过调整电感和电阻分量来获得比常规Q因子更好的Q因子，并且根据频率范围获得宽度范围从几十到几百的Q因子。

公开(公告)号：US07429874B2

公开(公告)日：2008-09-30

申请号：US11451962

申请日：2006-06-13

申请人： Sang Jin Byun ,  Hyun Kyu Yu

发明人： Sang Jin Byun ,  Hyun Kyu Yu

IPC分类号： H03K19/094

CPC分类号： H03F1/301 ,  H03F3/45183 ,  H03F2200/453 ,  H03F2200/456 ,  H03F2200/513

摘要： Provided is a replica bias circuit which is suitable for multi-layer stacked CMOS current mode logic (CML) and is stably used in application fields using a low power supply voltage. The replica bias circuit applies a reference voltage to gates of target transistors constituting an electronic circuit. The replica bias circuit includes a sub threshold voltage generator for maintaining a voltage difference lower than a threshold voltage of the transistor; and a replica path including devices designed by referring to dimensions of constituent devices forming a current flow path, the current flow path including the target transistors in the electronic circuit. With the replica bias circuit, multi-layer stacked CMOS current mode logic (CML) circuits can stably operate even at a low power supply voltage.

摘要翻译： 提供了一种适用于多层堆叠CMOS电流模式逻辑（CML）的复制偏置电路，并且在使用低电源电压的应用领域中稳定地使用。 复制偏置电路对构成电子电路的目标晶体管的栅极施加参考电压。 复制偏置电路包括用于保持低于晶体管的阈值电压的电压差的副阈值电压发生器; 以及包括通过参考形成电流流路的构成装置的尺寸而设计的装置的复制路径，所述电流流路包括电子电路中的目标晶体管。 利用复制偏置电路，即使在低电源电压下，多层堆叠CMOS电流模式逻辑（CML）电路也能稳定地工作。

公开(公告)号：US07420423B2

公开(公告)日：2008-09-02

申请号：US11431982

申请日：2006-05-11

申请人： Young Jae Lee ,  Hyun Kyu Yu

发明人： Young Jae Lee ,  Hyun Kyu Yu

IPC分类号： H03F3/04

CPC分类号： H03F3/189 ,  H03F3/45183 ,  H03F3/68

摘要： An active balun device is provided. The active balun device includes: a differential input portion for receiving an external single input signal to output two complementary differential signals; and a differential amplifier connected to the differential input portion in cascade to amplify the two differential signals received from the differential input portion. Thus, the active balun device has a sufficient gain and a desired bandwidth in a semiconductor circuit.

摘要翻译： 提供主动平衡 - 不平衡转换器。 主动平衡 - 不平衡变换器包括：差分输入部分，用于接收外部单个输入信号以输出两个互补差分信号; 以及级联连接到差分输入部分的差分放大器，以放大从差分输入部分接收的两个差分信号。 因此，有源平衡 - 不平衡转换器件在半导体电路中具有足够的增益和期望的带宽。

公开(公告)号：US07348849B2

公开(公告)日：2008-03-25

申请号：US11497461

申请日：2006-08-01

申请人： Seon Ho Han ,  Hyun Kyu Yu

发明人： Seon Ho Han ,  Hyun Kyu Yu

IPC分类号： H03F3/45 ,  H03G3/10

CPC分类号： H03G1/007 ,  H03F1/342 ,  H03F3/211 ,  H03F3/45206 ,  H03F3/45659 ,  H03F2200/15 ,  H03F2203/21154 ,  H03F2203/45008 ,  H03F2203/45302 ,  H03G7/06

摘要： A complementary metal oxide semiconductor (CMOS) variable gain amplifier has a wider decibel-linear gain variation characteristic with respect to a control voltage when a signal is amplified. The variable gain amplifier includes: a bias input circuit for supplying a current corresponding to a bias voltage; an operation region combination and feedback circuit connected to the bias input circuit and combining at least two amplifiers by feedback in response to a control voltage, each amplifier having a decibel-linear characteristic in saturation and triode regions of a complementary metal oxide semiconductor (CMOS); and a bias output circuit connected to the bias input circuit, and outputting bias current controlled by the operation region combination and feedback circuit.

摘要翻译： 互补金属氧化物半导体（CMOS）可变增益放大器在信号被放大时相对于控制电压具有更宽的分贝线性增益变化特性。 可变增益放大器包括：偏置输入电路，用于提供对应于偏置电压的电流; 连接到偏置输入电路的操作区域组合和反馈电路，并且通过响应于控制电压的反馈来组合至少两个放大器，每个放大器在互补金属氧化物半导体（CMOS）的饱和度和三极管区域中具有分贝线性特性， ; 以及偏置输出电路，连接到偏置输入电路，并输出由操作区域组合和反馈电路控制的偏置电流。