公开(公告)号：US07985697B2

公开(公告)日：2011-07-26

申请号：US12208512

申请日：2008-09-11

申请人： Jong Tae Moon ,  Yong Sung Eom ,  Min Ji Lee ,  Hyun Kyu Yu

发明人： Jong Tae Moon ,  Yong Sung Eom ,  Min Ji Lee ,  Hyun Kyu Yu

IPC分类号： H01L21/31

CPC分类号： H01L23/10 ,  B81B7/007 ,  B81C2203/0118 ,  H01L24/45 ,  H01L24/48 ,  H01L24/94 ,  H01L2224/16145 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/1461 ,  H01L2924/16235 ,  H01L2924/00 ,  H01L2924/2076 ,  H01L2224/05599

摘要： Provided are a wafer level package in which a communication line can be readily formed between an internal device and the outside of the package, and a method of fabricating the wafer level package. The wafer level package includes a first substrate having a cavity in which a first internal device is disposed, an Input/Output (I/O) pad formed on the first substrate and electrically connected with the first internal device, a second substrate disposed over the first substrate and from which a part corresponding to the I/O pad is removed, and a solder bonding the first and second substrates. According to the wafer level package and the method of fabricating the same, upper and lower substrates are sawed to different cutting widths, or a hole is formed in the upper substrate, such that a communication line of an internal device can be readily formed without a via process which penetrates a substrate. Therefore, in comparison with a conventional wafer level package fabricated using the via process, it is possible to simplify a fabrication process and reduce production cost.

摘要翻译： 提供了一种晶片级封装，其中可以容易地在内部器件和封装外部之间形成通信线，以及制造晶片级封装的方法。 晶片级封装包括具有第一内部器件的空腔的第一衬底，形成在第一衬底上并与第一内部器件电连接的输入/输出（I / O）焊盘，设置在第一衬底上的第二衬底 第一衬底并且从其中除去对应于I / O焊盘的部分，以及焊接第一和第二衬底的焊料。 根据晶片级封装及其制造方法，上下基板被切割成不同的切割宽度，或者在上基板上形成孔，使得可以容易地形成内部装置的连通线，而不需要 穿过基底的过程。 因此，与使用通孔工艺制造的常规晶片级封装相比，可以简化制造工艺并降低生产成本。

公开(公告)号：US20110018670A1

公开(公告)日：2011-01-27

申请号：US12648117

申请日：2009-12-28

申请人： Hyun-Cheol BAE ,  Kwang-Seong Choi ,  Yong Sung Eom ,  Jong Tae Moon ,  Moo Jung Chu ,  Jong-Hyun Lee

发明人： Hyun-Cheol BAE ,  Kwang-Seong Choi ,  Yong Sung Eom ,  Jong Tae Moon ,  Moo Jung Chu ,  Jong-Hyun Lee

IPC分类号： H01F5/00

CPC分类号： H01F17/0013 ,  H01F2017/002 ,  H01L2224/48091 ,  H01L2224/73257 ,  H01L2924/19107 ,  H01L2924/00014

摘要： Provided is an electronic device that includes an LTCC inductor including a first sheet disposed on a substrate and including a first conductive pattern, a second sheet disposed on the first sheet and including a second conductive pattern, and a via electrically connecting the first conductive pattern to the second conductive pattern, and a spacer disposed on a lower surface of the first sheet to provide an air gap between the substrate and the first sheet, wherein the first conductive pattern is exposed out of the lower surface of the first sheet.

摘要翻译： 提供一种电子设备，其包括LTCC电感器，其包括设置在基板上的第一片，并且包括第一导电图案，设置在第一片上并包括第二导电图案的第二片，以及将第一导电图案电连接到 第二导电图案和设置在第一片的下表面上的间隔件，以在基片和第一片之间提供气隙，其中第一导电图案从第一片的下表面露出。

公开(公告)号：US20100320596A1

公开(公告)日：2010-12-23

申请号：US12565171

申请日：2009-09-23

申请人： Yong Sung Eom ,  Kwang-Seong Choi ,  Hyun-Cheol Bae ,  Jong-Hyun Lee ,  Jong Tae Moon

发明人： Yong Sung Eom ,  Kwang-Seong Choi ,  Hyun-Cheol Bae ,  Jong-Hyun Lee ,  Jong Tae Moon

IPC分类号： H01L23/488 ,  H01L21/60

CPC分类号： H01L24/81 ,  H01L21/486 ,  H01L21/563 ,  H01L23/29 ,  H01L23/293 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/1134 ,  H01L2224/1152 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/81192 ,  H01L2224/818 ,  H01L2224/81801 ,  H01L2224/83194 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： Provided is a method for fabricating semiconductor package and a semiconductor package fabricated using the same. The method for fabricating semiconductor package dopes a mixture including the polymer material and the solder particle on the substrate in which the terminal is formed and applies heat, and thus the solder particle flows (or diffuses) toward the terminal in the heated polymer resin to adhere to the exposed surface of the terminal, i.e., the side surface and upper surface of the terminal, thereby forming the solder layer. The solder layer improves the adhesive strength between the terminal of the semiconductor chip and the terminal of the substrate in the subsequent flip chip bonding process.

摘要翻译： 提供一种制造半导体封装的方法和使用其制造的半导体封装。 制造半导体封装的方法在形成端子的基板上涂覆包括聚合物材料和焊料颗粒的混合物，并施加热量，从而焊料颗粒向加热的聚合物树脂中的端子流动（或扩散）以粘附 到端子的暴露表面，即端子的侧表面和上表面，从而形成焊料层。 焊料层在随后的倒装芯片接合工艺中提高了半导体芯片的端子和衬底的端子之间的粘合强度。

公开(公告)号：US08524571B2

公开(公告)日：2013-09-03

申请号：US13309582

申请日：2011-12-02

申请人： Jong Tae Moon ,  Yong Sung Eom ,  Hyun-Cheol Bae

发明人： Jong Tae Moon ,  Yong Sung Eom ,  Hyun-Cheol Bae

IPC分类号： H01L21/30 ,  H01L21/46 ,  H01L41/00

CPC分类号： B81C1/00293 ,  B81C2203/0145 ,  B81C2203/035 ,  H01L21/50 ,  H01L23/10 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/131 ,  H01L2224/16238 ,  H01L2224/291 ,  H01L2224/81815 ,  H01L2224/83815 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/1461 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/05552

摘要： Disclosed is a vacuum wafer level packaging method for a micro electro mechanical system device, including: forming a plurality of via holes on an upper wafer for protecting a micro electro mechanical system (MEMS) wafer; forming at least one metal layer on inner walls of the plurality of via holes and regions extended from the plurality of via holes; arranging and bonding the upper wafer and the MEMS wafer at atmospheric pressure; applying solder paste to the regions extended from the plurality of via holes; filling a solder in the plurality of via holes by increasing the temperature of a high-vacuum chamber to melt the solder paste; and changing the solder in the plurality of via holes to a solid state by lowering the temperature of the high-vacuum chamber.

摘要翻译： 公开了一种用于微机电系统装置的真空晶片级封装方法，包括：在上晶片上形成多个通孔，用于保护微机电系统（MEMS）晶片; 在所述多个通孔的内壁和从所述多个通孔延伸的区域中形成至少一个金属层; 在大气压下布置和粘合上晶片和MEMS晶片; 将焊膏施加到从所述多个通孔延伸的区域; 通过增加高真空室的温度来熔化焊膏，在多个通孔中填充焊料; 并且通过降低高真空室的温度将多个通孔中的焊料改变为固态。

公开(公告)号：US20120288983A1

公开(公告)日：2012-11-15

申请号：US13459560

申请日：2012-04-30

申请人： Moo Jung Chu ,  Ju Mi Kim ,  Yong Sung Eom ,  Ah Ram Jeon ,  Jong Tae Moon

发明人： Moo Jung Chu ,  Ju Mi Kim ,  Yong Sung Eom ,  Ah Ram Jeon ,  Jong Tae Moon

IPC分类号： H01L31/18

CPC分类号： H01G9/2081 ,  Y02E10/542 ,  Y02P70/521

摘要： Disclosed is a method for manufacturing a dye sensitized solar cell module. The method includes putting at least one or more heating-wires on an upper portion of an electrode of each solar cell sub-module; applying a metal paste on the upper portion of the electrode including at least one or more heating-wires; and heating and curing the metal paste by after overlapping the electrodes of a plurality of solar cell sub-modules each other, allowing a current to flow to at least one or more heating-wires.

摘要翻译： 公开了一种染料敏化太阳能电池模块的制造方法。 该方法包括在每个太阳能电池子模块的电极的上部放置至少一根或多根加热线; 在包括至少一个或多个加热丝的电极的上部上施加金属膏; 并且通过在多个太阳能电池子模块的电极彼此重叠之后加热和固化金属浆料，允许电流流向至少一个或多个加热线。

公开(公告)号：US20120161326A1

公开(公告)日：2012-06-28

申请号：US13330719

申请日：2011-12-20

申请人： Kwang-Seong Choi ,  Yong Sung Eom ,  Hyun-cheol Bae ,  Jong Tae Moon

发明人： Kwang-Seong Choi ,  Yong Sung Eom ,  Hyun-cheol Bae ,  Jong Tae Moon

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L21/76898 ,  H01L21/486 ,  H01L23/147 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/00

摘要： Provided is a composition for filling a Through Silicon Via (TSV) including: a metal powder; a solder powder; a curable resin; a reducing agent; and a curing agent. A TSV filling method using the composition and a substrate including a TSV plug formed of the composition are also provided.

摘要翻译： 提供了一种用于填充通硅（TSV）的组合物，其包括：金属粉末; 焊粉; 可固化树脂; 还原剂; 和固化剂。 还提供了使用该组合物的TSV填充方法和包含由该组合物形成的TSV塞的基板。

公开(公告)号：US08044757B2

公开(公告)日：2011-10-25

申请号：US12648117

申请日：2009-12-28

申请人： Hyun-Cheol Bae ,  Kwang-Seong Choi ,  Yong Sung Eom ,  Jong Tae Moon ,  Moo Jung Chu ,  Jong-Hyun Lee

发明人： Hyun-Cheol Bae ,  Kwang-Seong Choi ,  Yong Sung Eom ,  Jong Tae Moon ,  Moo Jung Chu ,  Jong-Hyun Lee

IPC分类号： H01F5/00 ,  H01F27/29 ,  H01F27/28 ,  H01L23/34 ,  H01L23/48

CPC分类号： H01F17/0013 ,  H01F2017/002 ,  H01L2224/48091 ,  H01L2224/73257 ,  H01L2924/19107 ,  H01L2924/00014

摘要： Provided is an electronic device that includes an LTCC inductor including a first sheet disposed on a substrate and including a first conductive pattern, a second sheet disposed on the first sheet and including a second conductive pattern, and a via electrically connecting the first conductive pattern to the second conductive pattern, and a spacer disposed on a lower surface of the first sheet to provide an air gap between the substrate and the first sheet, wherein the first conductive pattern is exposed out of the lower surface of the first sheet.

摘要翻译： 提供一种电子设备，其包括LTCC电感器，其包括设置在基板上的第一片，并且包括第一导电图案，设置在第一片上并包括第二导电图案的第二片，以及将第一导电图案电连接到 第二导电图案和设置在第一片的下表面上的间隔件，以在基片和第一片之间提供气隙，其中第一导电图案从第一片的下表面露出。

公开(公告)号：US20120222738A1

公开(公告)日：2012-09-06

申请号：US13411501

申请日：2012-03-02

申请人： Soo Young OH ,  Yong Sung Eom ,  Jong Tae Moon ,  Kwang Seong Choi

发明人： Soo Young OH ,  Yong Sung Eom ,  Jong Tae Moon ,  Kwang Seong Choi

IPC分类号： H01L31/0224 ,  H01L31/0232

CPC分类号： H01L31/022425 ,  H01B1/22 ,  H01L31/02168 ,  Y02E10/50

摘要： A conductive composition for a front electrode busbar of a silicon solar cell includes a metallic powder, a solder powder, a curable resin, a reducing agent, and a curing agent. A method of manufacturing a front electrode busbar of a silicon solar cell includes applying the composition to the front surface of the silicon solar cell wherein its front electrode finger line is formed. A substrate includes a front electrode busbar of a silicon solar cell, formed with a conductive composition. A silicon solar cell includes one or more electrodes containing a conductive composition including a conductive powder, a curable resin, a reducing agent, and a curing agent. A method of manufacturing the silicon solar cell includes forming a first electrode array with a first conductive composition, forming a second electrode, and forming a third electrode with a third conductive composition.

摘要翻译： 硅太阳能电池的前电极汇流条的导电组合物包括金属粉末，焊料粉末，固化树脂，还原剂和固化剂。 制造硅太阳能电池的前电极汇流条的方法包括将该组合物涂布在其前电极指线形成的硅太阳能电池的正面上。 基板包括由导电组合物形成的硅太阳能电池的前电极母线。 硅太阳能电池包括一个或多个包含导电组合物的电极，所述导电组合物包括导电粉末，可固化树脂，还原剂和固化剂。 制造硅太阳能电池的方法包括：用第一导电组合物形成第一电极阵列，形成第二电极，并用第三导电组合物形成第三电极。

公开(公告)号：US08030200B2

公开(公告)日：2011-10-04

申请号：US12565171

申请日：2009-09-23

申请人： Yong Sung Eom ,  Kwang-Seong Choi ,  Hyun-Cheol Bae ,  Jong-Hyun Lee ,  Jong Tae Moon

发明人： Yong Sung Eom ,  Kwang-Seong Choi ,  Hyun-Cheol Bae ,  Jong-Hyun Lee ,  Jong Tae Moon

IPC分类号： H01L21/44

CPC分类号： H01L24/81 ,  H01L21/486 ,  H01L21/563 ,  H01L23/29 ,  H01L23/293 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/1134 ,  H01L2224/1152 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/81192 ,  H01L2224/818 ,  H01L2224/81801 ,  H01L2224/83194 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A method for fabricating a semiconductor package, includes the steps of forming a first terminal at a first substrate; mixing a polymer resin and solder particles to provide a mixture; covering at least one of an upper surface and side surfaces of the first terminal with the mixture; and heating the first substrate at a temperature higher than a melting point of the solder particles of the mixture to form a solder layer that covers the at least one of an upper surface and a side surface of the first terminal. The solder particles flow or diffuse toward the terminal in the heated polymer resin to adhere to at least some of the exposed surfaces of the terminal thereby forming the solder layer. The solder layer improves the adhesive strength between the terminals of the semiconductor chip and the substrate in the subsequent flip chip bonding process.

摘要翻译： 一种半导体封装的制造方法，包括在第一基板上形成第一端子的工序; 混合聚合物树脂和焊料颗粒以提供混合物; 用所述混合物覆盖所述第一端子的上表面和侧表面中的至少一个; 以及在高于混合物的焊料颗粒的熔点的温度下加热第一衬底，以形成覆盖第一端子的上表面和侧表面中的至少一个的焊料层。 焊料颗粒朝向加热的聚合物树脂中的端子流动或扩散以粘附到端子的至少一些暴露表面，从而形成焊料层。 焊料层在随后的倒装芯片接合工艺中提高了半导体芯片的端子与衬底之间的粘合强度。

公开(公告)号：US20110089577A1

公开(公告)日：2011-04-21

申请号：US12761715

申请日：2010-04-16

申请人： Yong Sung Eom ,  Jong Tae Moon ,  Kwang-Seong Choi

发明人： Yong Sung Eom ,  Jong Tae Moon ,  Kwang-Seong Choi

IPC分类号： H01L23/498 ,  H01L21/60

CPC分类号： H01L25/50 ,  H01L24/29 ,  H01L2224/114 ,  H01L2224/1152 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/83101 ,  H01L2224/83138 ,  H01L2224/83191 ,  H01L2225/06513 ,  H01L2225/06575 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/15787 ,  H01L2924/01083 ,  H01L2924/00014 ,  H01L2924/00012

摘要： Provided is a method and structure for bonding a flip chip while increasing the manufacturing yield. In the method, solder bumps are formed on first electrodes and/or second electrodes disposed on first and second substrates, respectively. In addition, the first and second electrodes are arranged to face each other with a second resin including spacer balls being disposed between the first and second substrates. In addition, while flowing the second resin, the first and second substrates are pressed until the distance between the first and second substrates is decreased smaller than diameter of the spacer balls so as to connect the solder bumps between the first and second electrodes.

摘要翻译： 提供了一种在提高制造成品率的同时将倒装芯片接合的方法和结构。 在该方法中，分别在设置在第一和第二基板上的第一电极和/或第二电极上形成焊料凸点。 此外，第一和第二电极被布置成使第二树脂彼此面对，该第二树脂包括设置在第一和第二基板之间的间隔球。 此外，在流动第二树脂时，第一和第二基板被压制直到第一和第二基板之间的距离小于间隔球的直径，以便连接第一和第二电极之间的焊料凸块。