公开(公告)号：US20090140307A1

公开(公告)日：2009-06-04

申请号：US11947510

申请日：2007-11-29

申请人： Peter Baars ,  Andreas Eifler ,  Klaus Muemmler ,  Stefan Tegen

发明人： Peter Baars ,  Andreas Eifler ,  Klaus Muemmler ,  Stefan Tegen

IPC分类号： H01L29/94 ,  H01L21/44

CPC分类号： H01L29/66621 ,  H01L21/76877 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/4236

摘要： An integrated circuit includes a conductive line, the conductive line having a conductive layer made of a metal or a first compound including a metal and a capping layer made of a second compound comprising the metal, the capping layer being in contact with the conductive layer, the first compound being different from the second compound.

摘要翻译： 一种集成电路包括导线，该导线具有由金属构成的导电层或包含金属的第一化合物和由包含金属的第二化合物制成的覆盖层，所述覆盖层与导电层接触， 第一化合物与第二化合物不同。

公开(公告)号：US07371645B2

公开(公告)日：2008-05-13

申请号：US11321450

申请日：2005-12-30

申请人： Klaus Muemmler ,  Peter Baars ,  Stefan Tegen

发明人： Klaus Muemmler ,  Peter Baars ,  Stefan Tegen

IPC分类号： H01L21/336 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L29/66621 ,  H01L27/10876 ,  H01L29/4236 ,  H01L29/66545 ,  H01L29/66553

摘要： Fabrication of recessed channel array transistors (RCAT) with a corner gate device includes forming pockets between a semiconductor fin that includes a gate groove and neighboring shallow trench isolations that extend along longs sides of the semiconductor fin. A protection liner covers the semiconductor fin and the trench isolations in a bottom portion of the gate groove and the pockets. An insulator collar is formed in the exposed upper sections of the gate groove and the pockets, wherein a lower edge of the insulator collar corresponds to a lower edge of source/drain regions formed within the semiconductor fin. The protection liner is removed. The bottom portion of the gate groove and the pockets are covered with a gate dielectric and a buried gate conductor layer. The protection liner avoids residuals of polycrystalline silicon between the active area in the semiconductor fin and the insulator collar.

摘要翻译： 具有拐角栅极器件的凹槽通道阵列晶体管（RCAT）的制造包括在包括栅极沟槽的半导体鳍片之间形成凹穴以及沿着半导体鳍片的长边延伸的相邻浅沟槽隔离件。 保护衬套覆盖半导体鳍片和栅极沟槽和凹穴的底部中的沟槽隔离。 绝缘体套环形成在门槽和凹穴的暴露的上部中，其中绝缘体环的下边缘对应于形成在半导体鳍内的源/漏区的下边缘。 保护衬垫被取下。 栅极槽和凹穴的底部被栅极电介质和掩埋栅极导体层覆盖。 保护衬垫避免了半导体鳍片的有源区域和绝缘体套环之间的多晶硅残留。

公开(公告)号：US20070161277A1

公开(公告)日：2007-07-12

申请号：US11678735

申请日：2007-02-26

申请人： Peter Baars ,  Klaus Muemmler ,  Daniel Koehler

发明人： Peter Baars ,  Klaus Muemmler ,  Daniel Koehler

IPC分类号： H01R29/00

CPC分类号： H01L28/91 ,  H01L21/76816 ,  H01L27/10817 ,  H01L27/10894

摘要： A memory device includes an array of memory cells and a storage capacitor for storing information. Each memory cell includes an access transistor. The access transistor includes first and second source/drain regions, a channel disposed between the first and the second source/drain regions, and a gate electrode electrically insulated from the channel and adapted to control the conductivity of the channel. The access transistor is at least partially formed in the semiconductor substrate. The storage capacitor is adapted to be accessed by the access transistor. The storage capacitor includes at least first and second storage electrodes and at least a capacitor dielectric disposed between the first and the second storage electrodes. Each of the first and the second storage electrodes is disposed above the substrate surface.

摘要翻译： 存储器件包括存储单元阵列和用于存储信息的存储电容器。 每个存储单元包括存取晶体管。 存取晶体管包括第一和第二源极/漏极区域，设置在第一和第二源极/漏极区域之间的沟道以及与沟道电绝缘并适于控制沟道的导电性的栅电极。 存取晶体管至少部分地形成在半导体衬底中。 存储电容适于由存取晶体管访问。 存储电容器至少包括第一和第二存储电极以及设置在第一和第二存储电极之间的至少一个电容器电介质。 第一和第二存储电极中的每一个设置在基板表面上方。

公开(公告)号：US09484457B2

公开(公告)日：2016-11-01

申请号：US13404759

申请日：2012-02-24

申请人： Peter Baars ,  Till Schloesser

发明人： Peter Baars ,  Till Schloesser

IPC分类号： H01L21/74 ,  H01L29/78 ,  H01L27/108

CPC分类号： H01L29/7841 ,  H01L27/10802

摘要： A semiconductor device comprises a memory area including floating body transistors in the form of pillar structures, which are formed in a bulk architecture. The pillar structures may be appropriately addressed on the basis of a buried word line and a buried sense region or sense lines in combination with an appropriate bit line contact regime.

摘要翻译： 半导体器件包括存储区域，该存储器区域包括柱状结构形式的浮体晶体管，其以体积结构形式形成。 可以基于掩埋字线和掩埋感测区域或感测线路与适当的位线接触方式组合来适当地寻址支柱结构。

公开(公告)号：US09034753B2

公开(公告)日：2015-05-19

申请号：US13164272

申请日：2011-06-20

申请人： Till Schloesser ,  Peter Baars

发明人： Till Schloesser ,  Peter Baars

IPC分类号： H01L21/4763 ,  H01L27/108 ,  H01L21/768

CPC分类号： H01L27/10894 ,  H01L21/76816 ,  H01L21/76895 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10888

摘要： A method is disclosed that includes forming a conductive logic contact in a logic area of a semiconductor device, forming a bit line contact and a capacitor contact in a memory array of the semiconductor device, and performing at least one first common process to form a first metallization layer comprising a first conductive line in the logic area that is conductively coupled to the conductive logic contact and a bit line in the memory array that is conductively coupled to the bit line contact. The method further includes performing at least one second common process to form a second metallization layer comprising a first conductive structure conductively coupled to the first conductive line in the logic area and a second conductive structure in the memory array that that is conductively coupled to the capacitor contact.

摘要翻译： 公开了一种方法，其包括在半导体器件的逻辑区域中形成导电逻辑触点，在半导体器件的存储器阵列中形成位线接触和电容器触点，以及执行至少一个第一公共工艺以形成第一 金属化层包括在逻辑区域中的导电耦合到导电逻辑触点的第一导线和存储器阵列中与导线耦合到位线触点的位线。 所述方法还包括执行至少一个第二公共处理以形成第二金属化层，所述第二金属化层包括导电耦合到所述逻辑区域中的所述第一导电线的第一导电结构和所述存储器阵列中的导电耦合到所述电容器的第二导电结构 联系。

公开(公告)号：US09023696B2

公开(公告)日：2015-05-05

申请号：US13116672

申请日：2011-05-26

申请人： Peter Baars ,  Marco Lepper ,  Thilo Scheiper

发明人： Peter Baars ,  Marco Lepper ,  Thilo Scheiper

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L21/823871

摘要： Disclosed herein is a method of forming a semiconductor device. In one example, the method includes performing a first process operation to form a first etch stop layer above a first region of a semiconducting substrate where a first type of transistor device will be formed, and forming a first stress inducing layer at least above the first etch stop layer in the first region, wherein the first stress inducing layer is adapted to induce a stress in a channel region of the first type of transistor. The method further includes, after forming the first etch stop layer, performing a second process operation form a second etch stop layer above a second region of the substrate where a second type of transistor device will be formed, and forming a second stress inducing layer at least above the second etch stop layer in the second region, wherein the second stress inducing layer is adapted to induce a stress in a channel region of the second type of transistor. In one particular example, the first and second etch stop layers may have the same approximate thickness.

摘要翻译： 本文公开了形成半导体器件的方法。 在一个示例中，该方法包括执行第一处理操作以在半导体衬底的第一区域上方形成第一蚀刻停止层，其中将形成第一类型的晶体管器件，以及形成至少高于第一类型的第一应力诱导层 所述第一区域中的所述蚀刻停止层，其中所述第一应力诱导层适于在所述第一类型晶体管的沟道区域中引起应力。 该方法还包括：在形成第一蚀刻停止层之后，执行第二处理操作，形成第二蚀刻停止层，该第二蚀刻停止层位于衬底的第二区域的第二区域上方，在该第二区域将形成第二类型的晶体管器件，并且形成第二应力诱导层 至少在第二区域中的第二蚀刻停止层上方，其中第二应力诱导层适于在第二类型晶体管的沟道区域中引起应力。 在一个具体示例中，第一和第二蚀刻停止层可以具有相同的近似厚度。

公开(公告)号：US08846513B2

公开(公告)日：2014-09-30

申请号：US13241915

申请日：2011-09-23

申请人： Peter Baars ,  Richard Carter ,  Rolf Stephan

发明人： Peter Baars ,  Richard Carter ,  Rolf Stephan

IPC分类号： H01L21/3205 ,  H01L21/768 ,  H01L29/66 ,  H01L21/285 ,  H01L29/78

CPC分类号： H01L21/76897 ,  H01L21/28518 ,  H01L21/76814 ,  H01L29/66545 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

摘要： When forming self-aligned contact elements in sophisticated semiconductor devices in which high-k metal gate electrode structures are to be provided on the basis of a replacement gate approach, the self-aligned contact openings are filled with an appropriate fill material, such as polysilicon, while the gate electrode structures are provided on the basis of a placeholder material that can be removed with high selectivity with respect to the sacrificial fill material. In this manner, the high-k metal gate electrode structures may be completed prior to actually filling the contact openings with an appropriate contact material after the removal of the sacrificial fill material. In one illustrative embodiment, the placeholder material of the gate electrode structures is provided in the form of a silicon/germanium material.

摘要翻译： 当在基于更换栅极方法的高k金属栅电极结构的复杂半导体器件中形成自对准接触元件时，自对准接触开口用适当的填充材料填充，例如多晶硅 而栅电极结构基于可相对于牺牲填充材料以高选择性去除的占位符材料提供。 以这种方式，高k金属栅电极结构可以在去除牺牲填充材料之前用适当的接触材料实际填充接触开口之前完成。 在一个说明性实施例中，栅电极结构的占位符材料以硅/锗材料的形式提供。

公开(公告)号：US08722523B2

公开(公告)日：2014-05-13

申请号：US13371049

申请日：2012-02-10

申请人： Till Schloesser ,  Peter Baars ,  Frank Jakubowski

发明人： Till Schloesser ,  Peter Baars ,  Frank Jakubowski

IPC分类号： H01L29/772

CPC分类号： H01L29/78 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/288 ,  H01L21/76816 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： When forming sophisticated semiconductor devices including high-k metal gate electrode structures, a raised drain and source configuration may be used for controlling the height upon performing a replacement gate approach, thereby providing superior conditions for forming contact elements and also obtaining a well-controllable reduced gate height.

摘要翻译： 当形成包括高k金属栅电极结构的复杂半导体器件时，可以使用升高的漏极和源极配置来控制在执行替代栅极接近时的高度，从而为形成接触元件提供优越的条件，并且还获得良好可控的减小的 门高。

公开(公告)号：US08652889B2

公开(公告)日：2014-02-18

申请号：US13372837

申请日：2012-02-14

申请人： Andy Wei ,  Peter Baars ,  Richard Carter ,  Frank Ludwig

发明人： Andy Wei ,  Peter Baars ,  Richard Carter ,  Frank Ludwig

IPC分类号： H01L21/84 ,  H01L27/12 ,  H01L29/66

CPC分类号： H01L21/823807 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/1045 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

摘要： When forming sophisticated semiconductor devices, three-dimensional transistors in combination with planar transistors may be formed on the basis of a replacement gate approach and self-aligned contact elements by forming the semiconductor fins in an early manufacturing stage, i.e., upon forming shallow trench isolations, wherein the final electrically effective height of the semiconductor fins may be adjusted after the provision of self-aligned contact elements and during the replacement gate approach.

摘要翻译： 当形成复杂的半导体器件时，与平面晶体管组合的三维晶体管可以通过在早期制造阶段中形成半导体翅片（即，在形成浅沟槽隔离时）基于替代栅极接近和自对准接触元件而形成 其中半导体翅片的最终电有效高度可以在提供自对准接触元件之后和在更换栅极接近期间被调整。

公开(公告)号：US08518721B2

公开(公告)日：2013-08-27

申请号：US13471684

申请日：2012-05-15

申请人： Dmytro Chumakov ,  Peter Baars

发明人： Dmytro Chumakov ,  Peter Baars

IPC分类号： H01L21/00 ,  G01R31/26

CPC分类号： H01L21/31116 ,  H01L21/31053 ,  H01L22/12 ,  H01L22/26

摘要： A method is provided including depositing a layer of material on a substrate, during deposition of the material, at a predetermined depth, laterally implanting a first dopant and a second dopant in the material, the second dopant being different from the first dopant, etching the material, during etching, detecting the positions and intensities of the first and second dopants, and calculating lateral homogeneity of the material in situ from the intensities of the first and second dopants.

摘要翻译： 提供了一种方法，包括在材料沉积期间在预定深度沉积衬底上的材料层，在材料中横向注入第一掺杂剂和第二掺杂剂，第二掺杂剂不同于第一掺杂剂，蚀刻 材料，在蚀刻期间，检测第一和第二掺杂剂的位置和强度，以及从第一和第二掺杂剂的强度计算原位材料的侧向均匀性。