公开(公告)号：US20110044384A1

公开(公告)日：2011-02-24

申请号：US12939031

申请日：2010-11-03

Applicant: David Kyong-Sik Chung ,  Afshin Momtaz

Inventor： David Kyong-Sik Chung ,  Afshin Momtaz

IPC: H03H7/30

CPC classification number: H04L25/03878 ,  H04L25/03146

Abstract: An equalization circuit adjusts (e.g., equalizes) an input signal according to the value of one or more adjustment signals (e.g., equalization coefficients) without a multiplication operation. For example, the circuit may add or subtract a value of a coefficient signal to the amplitude of an input signal. Here, whether the coefficient is added or subtracted may depend on the sign of a control signal.

Abstract translation: 均衡电路根据一个或多个调整信号的值（例如，均衡系数）调整（例如，均衡）输入信号而不进行乘法运算。 例如，电路可以将系数信号的值加到或减去输入信号的幅度。 这里，系数是否被相加或取决于控制信号的符号。

公开(公告)号：US20110031996A1

公开(公告)日：2011-02-10

申请号：US12904524

申请日：2010-10-14

Applicant: Afshin Momtaz

Inventor： Afshin Momtaz

IPC: H03K17/16 ,  H04B3/28

CPC classification number: G06F1/10

Abstract: According to one general aspect, an apparatus may include a clock channel, a shielding tunnel, and clock repeaters. In various embodiments, the clock channel may be configured to carry the clock signal, and may include a portion of a metal layer of an integrated circuit. In some embodiments, the shielding tunnel may be configured to shield, in at least four directions, the clock channel from other signals, and may include portions of a at least three metal layers of the integrated circuit. The shielding tunnel may be connected to the positive and negative supplies in order to provide the required power for the clock repeaters.

Abstract translation: 根据一个一般方面，装置可以包括时钟信道，屏蔽隧道和时钟中继器。 在各种实施例中，时钟信道可以被配置为承载时钟信号，并且可以包括集成电路的金属层的一部分。 在一些实施例中，屏蔽隧道可以被配置为在至少四个方向上屏蔽来自其它信号的时钟信道，并且可以包括集成电路的至少三个金属层的部分。 屏蔽通道可以连接到正极和负极供电，以便为时钟转发器提供所需的电源。

公开(公告)号：US07822113B2

公开(公告)日：2010-10-26

申请号：US10823252

申请日：2004-04-13

Applicant: Davide Tonietto ,  Afshin Momtaz

Inventor： Davide Tonietto ,  Afshin Momtaz

IPC: H03H7/30

CPC classification number: H04L25/03057 ,  H03L7/0807 ,  H03L7/0891 ,  H03L7/091 ,  H04L7/0087 ,  H04L7/033 ,  H04L2025/0349

Abstract: In an integrated decision feedback equalizer and clock and data recovery circuit one or more flip-flops and/or latches may be shared. One or more flip-flops and/or latches may be used in retiming operations in a decision feedback equalizer and in phase detection operations in a clock recovery circuit. Outputs of the flip-flops and/or latches may be used to generate feedback signals for the decision feedback equalizer. The output of a flip-flop and/or latches may be used to generate signals that drive a charge pump in the clock recovery circuit.

Abstract translation: 在集成判决反馈均衡器和时钟和数据恢复电路中，可以共享一个或多个触发器和/或锁存器。 一个或多个触发器和/或锁存器可用于判决反馈均衡器中的重新定时操作和时钟恢复电路中的相位检测操作。 可以使用触发器和/或锁存器的输出来产生用于判决反馈均衡器的反馈信号。 触发器和/或锁存器的输出可用于产生驱动时钟恢复电路中的电荷泵的信号。

公开(公告)号：US20100182045A1

公开(公告)日：2010-07-22

申请号：US12555564

申请日：2009-09-08

Applicant: Afshin Momtaz

Inventor： Afshin Momtaz

IPC: H03K19/00 ,  H03L7/00

CPC classification number: G06F1/10

Abstract: According to one general aspect, an apparatus may include a clock channel, a shielding tunnel, and clock repeaters. In various embodiments, the clock channel may be configured to carry the clock signal, and may include a portion of a metal layer of an integrated circuit. In some embodiments, the shielding tunnel may be configured to shield, in at least four directions, the clock channel from other signals, and may include portions of a at least three metal layers of the integrated circuit. The shielding tunnel may be connected to the positive and negative supplies in order to provide the required power for the clock repeaters.

Abstract translation: 根据一个一般方面，装置可以包括时钟信道，屏蔽隧道和时钟中继器。 在各种实施例中，时钟信道可以被配置为承载时钟信号，并且可以包括集成电路的金属层的一部分。 在一些实施例中，屏蔽隧道可以被配置为在至少四个方向上屏蔽来自其它信号的时钟信道，并且可以包括集成电路的至少三个金属层的部分。 屏蔽通道可以连接到正极和负极供电，以便为时钟转发器提供所需的电源。

公开(公告)号：US07688237B2

公开(公告)日：2010-03-30

申请号：US12000757

申请日：2007-12-17

Applicant: Jun Cao ,  Afshin Momtaz

Inventor： Jun Cao ,  Afshin Momtaz

IPC: H03M1/10

CPC classification number: H03M1/1061 ,  H03M1/362

Abstract: Methods, systems, and apparatuses for calibration of analog to digital converters (ADC) are described herein. In an aspect, an ADC includes a plurality of slices. Each slice includes a digital to analog converter (DAC), a comparator, and a digital processing unit (DPU). The digital processing unit is electrically connected to the comparator and the DAC. In another aspect, an analog-to-digital converter includes an input module and an analog to digital converter core configured to receive an analog input from the input module and generate a digital output. The ADC is configured to adjust a precision of the analog to digital converter core based on a quality of the analog input signal.

Abstract translation: 本文描述了用于模数转换器（ADC）的校准的方法，系统和装置。 在一方面，ADC包括多个切片。 每个片包括数模转换器（DAC），比较器和数字处理单元（DPU）。 数字处理单元电连接到比较器和DAC。 在另一方面，模数转换器包括被配置为从输入模块接收模拟输入并产生数字输出的输入模块和模数转换器内核。 ADC配置为基于模拟输入信号的质量来调整模数转换器内核的精度。

公开(公告)号：US20090230993A1

公开(公告)日：2009-09-17

申请号：US12049701

申请日：2008-03-17

Applicant: Afshin Momtaz

Inventor： Afshin Momtaz

IPC: H03K19/0175 ,  H03K3/00

CPC classification number: H03K19/017509

Abstract: Low power high-speed output driver. An array of switches (some of which are inverting switches whose connectivity is governed oppositely as the control signal provided to it) is implemented such that an input signal governs the connectivity of those switches. A resistor is coupled between the nodes interposed between the switches of the array, and an output signal is taken from the nodes at ends of the resistor. The high voltage level of such an output driver is truly the level of the power supply energizing the circuit (e.g., VDD) while still consuming relatively low power.

Abstract translation: 低功耗高速输出驱动。 一组开关（其中一些是反向开关，其连接性与提供给它的控制信号相反地控制），使得输入信号控制这些开关的连接。 电阻器耦合在插入阵列的开关之间的节点之间，并且从电阻器端部处的节点获取输出信号。 这种输出驱动器的高电压电平实际上是在仍然消耗相对较低的功率的情况下为电路供电（例如，VDD）的电源的电平。

公开(公告)号：US07525470B2

公开(公告)日：2009-04-28

申请号：US11845765

申请日：2007-08-27

Applicant: Vasudevan Parthasarthy ,  Sudeep Bhoja ,  Vivek Telang ,  Afshin Momtaz

Inventor： Vasudevan Parthasarthy ,  Sudeep Bhoja ,  Vivek Telang ,  Afshin Momtaz

IPC: H03M1/12

CPC classification number: H03M1/0836 ,  H03M1/1215 ,  H03M1/183

Abstract: Embodiments include a system for performing dispersion compensation on an electromagnetic signal received over a communication channel, the electromagnetic signal bearing information at a symbol rate. An interleaved analog to digital converter (“ADC”) block may be used, wherein the interleaved ADC block may be configured to generate a plurality of digitally sampled signals from the electromagnetic signal. An interleaved equalizer block may be configured to digitally process each of the digitally sampled signals generated by the ADC block to generate a plurality of digitally equalized signals. A multiplexer may be configured to aggregate the digitally equalized signals into a composite output signal.

Abstract translation: 实施例包括一种用于对通过通信信道接收的电磁信号进行色散补偿的系统，该电磁信号以符号速率承载信息。 可以使用交错模数转换器（“ADC”）块，其中交织的ADC块可以被配置为从电磁信号生成多个数字采样的信号。 交织的均衡器块可以被配置为数字地处理由ADC块产生的数字采样信号中的每一个以产生多个数字均衡的信号。 多路复用器可以被配置为将数字均衡的信号聚合成复合输出信号。

公开(公告)号：US20080152062A1

公开(公告)日：2008-06-26

申请号：US11705316

申请日：2007-02-12

Applicant: Namik K. Kocaman ,  Afshin Momtaz

Inventor： Namik K. Kocaman ,  Afshin Momtaz

IPC: H04L7/02

CPC classification number: H04L7/033 ,  H04L7/0008

Abstract: Multiple channel synchronized clock generation scheme. A novel approach is presented herein in which synchronized clock signals are generated that can be used in parallel processing of deserialized signals. When a serial input signal is received, it can be deserialized into a plurality of parallel signals, and each of these parallel signals can be processed at a frequency that is lower than the frequency of the serial signal. Overall, the frequency at which all of the parallel signals are processed can be the same or substantially close to the frequency of the serial signal, so that throughput within a communication system is not compromised or undesirably reduced. This novel approach is operable to perform independent adjustment of the operational parameters within an apparatus that is operable to perform multiple channel synchronized clock generation (e.g., phase rotation and/or division of signals within each of the individual channels can be adjusted independently).

Abstract translation: 多通道同步时钟生成方案。 本文提出了一种新颖的方法，其中产生可以并行处理反序列化信号的同步时钟信号。 当串行输入信号被接收时，它可以被反序列化成多个并行信号，并且这些并行信号中的每一个可以以低于串行信号频率的频率进行处理。 总的来说，所有并行信号被处理的频率可以相同或基本上接近串行信号的频率，使得通信系统内的吞吐量不会受到损害或不期望地减少。 这种新颖的方法可操作以对可操作以执行多信道同步时钟生成的装置中的操作参数进行独立调整（例如，可以独立地调整各个信道内的信号的相位旋转和/或除法）。

公开(公告)号：US07386085B2

公开(公告)日：2008-06-10

申请号：US10159788

申请日：2002-05-30

Applicant: Afshin Momtaz ,  Kambiz Vakilian

Inventor： Afshin Momtaz ,  Kambiz Vakilian

IPC: H04L7/033

CPC classification number: H03L7/081 ,  H03L7/0891 ,  H03L7/093 ,  H04L7/033

Abstract: A closed-loop circuitry includes, in part, a loop filter and a current source/sink coupled to the loop filter to adjust the phase/frequency of the signal generated by the closed-loop circuitry. Because the voltage generated by the loop filter has a relatively low frequency, the current source/sink is operable at a relatively low frequency. Each current source and current sink may be a current digital-to-analog (DAC). The amount of current sourced into or sunk out of the loop filter by the current DAC is varied by setting the associated bits of a multi-bit signal. If the closed-loop circuitry is differential, a current source is coupled to the loop filter adapted to receive the differentially high signal, and a current source is coupled to the loop filter adapted to receive the differentially low signal.

Abstract translation: 闭环电路部分地包括环路滤波器和耦合到环路滤波器的电流源/宿，以调整由闭环电路产生的信号的相位/频率。 由于环路滤波器产生的电压具有相对低的频率，所以电流源/汇可以相对较低的频率工作。 每个电流源和电流吸收器可以是当前的数模（DAC）。 通过设置当前DAC的环路滤波器中的电流或者从环路滤波器中吸出的电流量可通过设置多位信号的相关位来改变。 如果闭环电路是差分的，则电流源耦合到适于接收差分高信号的环路滤波器，并且电流源耦合到适于接收差分低信号的环路滤波器。

公开(公告)号：US20080049847A1

公开(公告)日：2008-02-28

申请号：US11837278

申请日：2007-08-10

Applicant: Vivek Telang ,  Vasudevan Parthasarathy ,  Sudeep Bhoja ,  Hong Chen ,  Afshin Momtaz ,  Chung-Jue Chen ,  Ali Ghiasi ,  Michael Furlong ,  Lorenzo Longo

Inventor： Vivek Telang ,  Vasudevan Parthasarathy ,  Sudeep Bhoja ,  Hong Chen ,  Afshin Momtaz ,  Chung-Jue Chen ,  Ali Ghiasi ,  Michael Furlong ,  Lorenzo Longo

IPC: H04B14/04

CPC classification number: H04L25/03063 ,  H04B10/25133 ,  H04B10/697 ,  H04L7/0087 ,  H04L7/033 ,  H04L25/0307 ,  H04L2025/03356 ,  H04L2025/0349 ,  H04L2025/03509

Abstract: Embodiments include a system for performing dispersion compensation on an electromagnetic signal received over a communication channel, the electromagnetic signal bearing information at a symbol rate. An interleaved analog to digital converter (“ADC”) block may be used, wherein the interleaved ADC block may be configured to generate a plurality of digitally sampled signals from the electromagnetic signal. An interleaved equalizer block may be configured to digitally process each of the digitally sampled signals generated by the ADC block to generate a plurality of digitally equalized signals. A multiplexer may be configured to aggregate the digitally equalized signals into a composite output signal.

Abstract translation: 实施例包括一种用于对通过通信信道接收的电磁信号进行色散补偿的系统，该电磁信号以符号速率承载信息。 可以使用交错模数转换器（“ADC”）块，其中交织的ADC块可以被配置为从电磁信号生成多个数字采样的信号。 交织的均衡器块可以被配置为数字地处理由ADC块产生的数字采样信号中的每一个以产生多个数字均衡的信号。 多路复用器可以被配置为将数字均衡的信号聚合成复合输出信号。