公开(公告)号：US20200176513A1

公开(公告)日：2020-06-04

申请号：US16205314

申请日：2018-11-30

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Lanxiang WANG ,  Shyue Seng TAN ,  Eng Huat TOH

IPC: H01L27/24 ,  H01L45/00

Abstract: A memory device may include a substrate having conductivity regions and a channel region. A first voltage line may be arranged over the channel region. A second voltage line, and third and fourth voltage lines may be electrically coupled to a first conductivity region and a second conductivity region respectively. Resistive units may be arranged between the third and fourth voltage lines and the second conductivity region. In use, changes in voltages applied between the second and third voltage lines, and between the second and fourth voltage lines may cause resistances of first and second resistive units to switch between lower and higher resistance values. The lower resistance value of the first resistive unit may be different from the lower resistance value of the second resistive unit and/or the higher resistance value of the first resistive unit may be different from the higher resistance value of the second resistive unit.

公开(公告)号：US20190312046A1

公开(公告)日：2019-10-10

申请号：US15947488

申请日：2018-04-06

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Anson HERYANTO ,  Eng Huat TOH ,  Yongshun SUN ,  Yoke Leng LIM ,  Siow Lee CHWA

IPC: H01L27/11524 ,  H01L27/11558 ,  H01L21/8239

Abstract: Method for forming a memory device are disclosed. Embodiments include forming memory cells over a substrate, each memory cell includes a control gate (CG) formed over a floating gate (FG) and a select gate (SG) formed adjacent to a first side of the CG and FG, wherein a vertical oxide layer is formed between the SG and the CG and FG, forming an implant mask layer over a portion of the SG, CG and vertical oxide of each memory cell; and implanting dopants into the substrate using the implant mask to form source drain (S/D) regions between the memory cells.

公开(公告)号：US20190259936A1

公开(公告)日：2019-08-22

申请号：US16399393

申请日：2019-04-30

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Bin LIU ,  Eng Huat TOH ,  Ruchil Kumar JAIN

IPC: H01L43/04 ,  G01R33/00 ,  G01R33/02 ,  G01R33/07 ,  H01L43/14 ,  H01L43/06

Abstract: A method of forming a 3D Hall effect sensor and the resulting device are provided. Embodiments include forming a p-type well in a substrate; forming a first n-type well in a first region surrounded by the p-type well in top view; forming a second n-type well in a second region surrounding the p-type well; providing n-type dopant in the first and second n-type wells; and providing p-type dopant in the p-type well and the first n-type well.

公开(公告)号：US20190115441A1

公开(公告)日：2019-04-18

申请号：US15730745

申请日：2017-10-12

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Shyue Seng TAN ,  Kiok Boone Elgin QUEK ,  Eng Huat TOH

IPC: H01L29/49 ,  H01L23/535 ,  H01L29/51 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66 ,  H01L23/522

CPC classification number: H01L29/4983 ,  H01L21/28291 ,  H01L21/823468 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/535 ,  H01L29/40111 ,  H01L29/408 ,  H01L29/512 ,  H01L29/516 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/78391

Abstract: A semiconductor device with reduce capacitance coupling effect which can reduce the overall parasitic capacitances is disclosed. The semiconductor device includes a gate sidewall spacer with a negative capacitance dielectric layer with and without a dielectric layer. The semiconductor device may also include a plurality of interlevel dielectric (ILD) with a layer of negative capacitance dielectric layer followed by a dielectric layer disposed in-between metal lines in any ILD and combinations. The negative capacitance dielectric layer includes a ferroelectric material which has calculated and selected thicknesses with desired negative capacitance to provide optimal total overlap capacitance in the circuit component which aims to reduce the overall capacitance coupling effect.

公开(公告)号：US20180374893A1

公开(公告)日：2018-12-27

申请号：US15630534

申请日：2017-06-22

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Eng Huat TOH ,  Yinjie DING ,  Kangho LEE

IPC: H01L27/22 ,  H01L43/08 ,  H01L43/12

Abstract: A method of forming a differential sensing STT MRAM design and the resulting device are provided. Embodiments include rows of programmable cells formed in a magnetoresistive random-access memory (MRAM) device, each row having a source line (SL); and rows of complimentary cells formed in the MRAM device, each row having a SL, wherein a SL of a row of programmable cells and a SL of a row of complimentary cells of a pair of rows form a merged SL.

公开(公告)号：US20180374850A1

公开(公告)日：2018-12-27

申请号：US16040105

申请日：2018-07-19

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Ming ZHU ,  Pinghui LI ,  Su Yi Susan YEOW ,  Yiang Aun NGA ,  Danny Pak-Chum SHUM ,  Eng Huat TOH

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/02

Abstract: Methods for preventing step-height difference of flash and logic gates in FinFET devices and related devices are provided. Embodiments include forming fins in flash and logic regions; recessing an oxide exposing an upper portion of the fins; forming an oxide liner over the upper portion in the flash region; forming a polysilicon gate over and perpendicular to the fins in both regions; removing the gate from the logic region and patterning the gate in the flash region forming a separate gate over each fin; forming an ONO layer over the gates in the flash region; forming a second polysilicon gate over and perpendicular to the fins in both regions; planarizing the second polysilicon gate exposing a portion of the ONO layer over the gates in the flash region; forming and patterning a hardmask, exposing STI regions between the flash and logic regions; and forming an ILD over the STI regions.

公开(公告)号：US20180198061A1

公开(公告)日：2018-07-12

申请号：US15402799

申请日：2017-01-10

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Eng Huat TOH ,  Ruchil Kumar JAIN ,  Yongshun SUN ,  Shyue Seng TAN

IPC: H01L43/06 ,  H01L43/04 ,  H01L43/14 ,  G01R33/07

CPC classification number: H01L43/065 ,  G01R33/07 ,  H01L43/04 ,  H01L43/14

Abstract: A method of forming a 3D Hall effect sensor and the resulting device are provided. Embodiments include forming a p-type well in a substrate; forming a first n-type well in a first region surrounded by the p-type well in top view; forming a second n-type well in a second region surrounding the p-type well; implanting n-type dopant in the first and second n-type wells; and implanting p-type dopant in the p-type well and the first n-type well.

公开(公告)号：US20180033963A1

公开(公告)日：2018-02-01

申请号：US15729314

申请日：2017-10-10

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Eng Huat TOH ,  Elgin QUEK ,  Shyue Seng TAN

IPC: H01L45/00 ,  H01L27/24

Abstract: A method of fabricating a fin selector with a gated RRAM and the resulting device are disclosed. Embodiments include forming a bottom electrode layer and a hardmask on a semiconductor substrate; etching the hardmask, bottom electrode layer, and semiconductor substrate to form a fin-like structure; forming first and second dummy gate stacks on first and second side surfaces of the fin-like structure, respectively; forming spacers on vertical surfaces of the first and second dummy gate stacks; forming an ILD surrounding the spacers; removing the first and second dummy gate stacks, forming first and second cavities on first and second sides of the fin-like structure; forming an RRAM layer on the first and second side surfaces of the fin-like structure in the first and second cavities, respectively; and filling each of the first and second cavities with a top electrode.

公开(公告)号：US20170345830A1

公开(公告)日：2017-11-30

申请号：US15674558

申请日：2017-08-11

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Ping ZHENG ,  Eng Huat TOH ,  Kiok Boone Elgin QUEK ,  Yuan SUN

IPC: H01L27/112 ,  H01L29/06 ,  H01L29/786 ,  H01L29/66 ,  H01L29/423 ,  B82Y40/00 ,  B82Y10/00

CPC classification number: H01L27/11206 ,  B82Y10/00 ,  B82Y40/00 ,  H01L23/5252 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/7851 ,  H01L29/7853 ,  Y10S977/765 ,  Y10S977/888 ,  Y10S977/943

Abstract: Devices and methods for forming a device are presented. The method includes providing a substrate prepared with at least a first region for accommodating an anti-fuse based memory cell. A fin structure is formed in the first region. The fin structure includes top and bottom fin portions and includes channel and non-channel regions defined along the length of the fin structure. An isolation layer is formed on the substrate. The isolation layer has a top isolation surface disposed below a top fin surface, leaving the top fin portion exposed. At least a portion of the exposed top fin portion in the channel region is processed to form a sharpened tip profile at top of the fin. A gate having a gate dielectric and a metal gate electrode is formed over the substrate. The gate wraps around the channel region of the fin structure.

公开(公告)号：US20170069619A1

公开(公告)日：2017-03-09

申请号：US14848364

申请日：2015-09-09

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Eng Huat TOH ,  Kiok Boone Elgin QUEK

IPC: H01L27/02 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0266 ,  H01L27/0274 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/66492 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/7833 ,  H01L29/7835

Abstract: A gate-grounded metal oxide semiconductor (GGMOS) device is disclosed. The GGMOS is an n-type (GGNMOS) transistor used as an electrostatic discharge (ESD) protection device. The GGMOS includes a base extension region under an elevated source. The elevated source and base extension regions increase Leff and reduce beta, increasing performance of the ESD protection.

Abstract translation: 公开了一种栅极接地金属氧化物半导体（GGMOS）器件。 GGMOS是用作静电放电（ESD）保护装置的n型（GGNMOS）晶体管。 GGMOS包括在升高的源下的基本扩展区域。 源极和基极扩展区域增加了Leff并降低了beta，提高了ESD保护的性能。