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    SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING THE SAME
    91.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20110272736A1

    公开(公告)日：2011-11-10

    申请号：US13102860

    申请日：2011-05-06

    申请人： JONGHO LEE ,  Chang-Bong Oh ,  Ho Lee ,  Myungsun Kim

    发明人： JONGHO LEE ,  Chang-Bong Oh ,  Ho Lee ,  Myungsun Kim

    IPC分类号： H01L29/165

    CPC分类号： H01L21/823807 ,  H01L21/28238 ,  H01L21/823412 ,  H01L21/823462 ,  H01L21/823857 ,  H01L29/513 ,  H01L29/517

    摘要： A semiconductor device includes a substrate including a first region and a second region each having an n-type region and a p-type region, wherein the n-type region in the first region includes a silicon channel, the p-type region in the first region includes a silicon germanium channel, and the n-type region and the p-type region in the second region respectively include a silicon channel. A first gate insulating pattern formed of a thermal oxide layer is disposed on the substrate of the n-type and p-type regions in the second region.

    摘要翻译： 半导体器件包括：衬底，包括第一区域和第二区域，每个区域具有n型区域和p型区域，其中第一区域中的n型区域包括硅沟道， 第一区域包括硅锗沟道，并且第二区域中的n型区域和p型区域分别包括硅沟道。 在第二区域中的n型和p型区域的基板上设置由热氧化物层形成的第一栅极绝缘图案。

    METHODS OF FABRICATING INTEGRATED CIRCUIT DEVICES INCLUDING STRAINED CHANNEL REGIONS AND RELATED DEVICES
    93.
    发明申请
    METHODS OF FABRICATING INTEGRATED CIRCUIT DEVICES INCLUDING STRAINED CHANNEL REGIONS AND RELATED DEVICES 有权
    制作集成电路设备的方法，包括应变通道区域和相关设备

    公开(公告)号：US20100203692A1

    公开(公告)日：2010-08-12

    申请号：US12763654

    申请日：2010-04-20

    申请人： Ki-chul Kim ,  Ho Lee ,  Jung-deog Lee

    发明人： Ki-chul Kim ,  Ho Lee ,  Jung-deog Lee

    IPC分类号： H01L21/8238 ,  H01L21/04

    CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/0653 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7848

    摘要： A method of fabricating an integrated circuit device includes forming first and second gate patterns on surfaces of a semiconductor substrate in PMOS and NMOS regions, respectively, of the substrate. P-type source/drain regions are epitaxially grown on opposite sides of the first gate pattern in the PMOS region to exert compressive stress on a first channel region therebetween adjacent the first gate pattern. N-type source/drain regions are epitaxially grown on opposite sides of the second gate pattern in the NMOS region to exert tensile stress on a second channel region therebetween adjacent the second gate pattern. Related devices are also discussed.

    摘要翻译： 一种制造集成电路器件的方法包括分别在衬底的PMOS和NMOS区域中的半导体衬底的表面上形成第一和第二栅极图案。 P型源极/漏极区域在PMOS区域中的第一栅极图案的相对侧上外延生长，以在邻近第一栅极图案的第一沟道区域上施加压应力。 N型源极/漏极区域在NMOS区域中的第二栅极图案的相对侧上外延生长，以在邻近第二栅极图案的第二沟道区域上施加拉伸应力。 还讨论了相关设备。

    METHOD OF FORMING A SEMICONDUCTOR DEVICE HAVING AN EPITAXIAL SOURCE/DRAIN
    94.
    发明申请
    METHOD OF FORMING A SEMICONDUCTOR DEVICE HAVING AN EPITAXIAL SOURCE/DRAIN 审中-公开
    形成具有外来源/排水的半导体器件的方法

    公开(公告)号：US20100171181A1

    公开(公告)日：2010-07-08

    申请号：US12640944

    申请日：2009-12-17

    申请人： Hwa Sung Rhee ,  Myung Sun Kim ,  Ho Lee ,  Hoi Sung Chung

    发明人： Hwa Sung Rhee ,  Myung Sun Kim ,  Ho Lee ,  Hoi Sung Chung

    IPC分类号： H01L27/06 ,  H01L21/8238

    CPC分类号： H01L21/26506 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

    摘要： A method of forming a semiconductor device includes forming a device isolation region in a silicon substrate to define an nMOS region and a pMOS region. A p-well is formed in the nMOS region and an n-well in the pMOS region. Gate structures are formed over the p-well and n-well, each gate structure including a stacked structure comprising a gate insulating layer and a gate electrode. A resist mask covers the nMOS region and exposes the pMOS region. Trenches are formed in the substrate on opposite sides of the gate structures of the pMOS region. SiGe layers are grown in the trenches of the pMOS region. The resist mask is removed from the nMOS region. Carbon is implanted to an implantation depth simultaneously on both the nMOS region and the pMOS region to form SiC on the nMOS region and SiGe on the pMOS region.

    摘要翻译： 形成半导体器件的方法包括在硅衬底中形成器件隔离区以限定nMOS区和pMOS区。 在nMOS区域中形成p阱，在pMOS区域中形成n阱。 栅极结构形成在p阱和n阱上，每个栅极结构包括包括栅极绝缘层和栅电极的堆叠结构。 抗蚀剂掩模覆盖nMOS区域并暴露pMOS区域。 沟槽形成在pMOS区域的栅极结构的相对侧上的衬底中。 SiGe层生长在pMOS区域的沟槽中。 从nMOS区域去除抗蚀剂掩模。 在nMOS区域和pMOS区域上同时植入碳到注入深度，以在nMOS区域上形成SiC，在pMOS区域上形成SiGe。

    Method of Manufacturing a Semiconductor Device
    97.
    发明申请
    Method of Manufacturing a Semiconductor Device 有权
    制造半导体器件的方法

    公开(公告)号：US20090170254A1

    公开(公告)日：2009-07-02

    申请号：US12343134

    申请日：2008-12-23

    申请人： Hwa-Sung Rhee ,  Ho Lee ,  Myung-Sun Kim ,  Ji-Hye Yi

    发明人： Hwa-Sung Rhee ,  Ho Lee ,  Myung-Sun Kim ,  Ji-Hye Yi

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L21/26506 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

    摘要： In a method of manufacturing a semiconductor device, a first gate electrode and a second gate electrode are formed in a first area and a second area of a substrate. Non-crystalline regions are formed in the first area of the substrate adjacent the first gate electrode. A layer having a first stress is formed on the substrate and the first and the second gate electrodes. A mask is formed on a first portion of the layer in the first area of the substrate to expose a second portion of the layer in the second area. The second portion is etched to form a sacrificial spacer on a sidewall of the second gate electrode. The second area of the substrate is partially etched using the mask, the second gate electrode and the sacrificial spacer, to form recesses in the second area of the substrate adjacent the second gate electrode. Patterns having a second stress are formed in the recesses.

    摘要翻译： 在制造半导体器件的方法中，第一栅电极和第二栅电极形成在衬底的第一区域和第二区域中。 在与第一栅电极相邻的衬底的第一区域中形成非结晶区域。 在基板和第一和第二栅电极上形成具有第一应力的层。 掩模在衬底的第一区域中的该层的第一部分上形成以暴露第二区域中该层的第二部分。 蚀刻第二部分以在第二栅电极的侧壁上形成牺牲间隔物。 使用掩模，第二栅电极和牺牲隔离物部分蚀刻衬底的第二区域，以在与第二栅电极相邻的衬底的第二区域中形成凹陷。 在凹部中形成具有第二应力的图案。

    Passivation layer assembly on a substrate and display substrate having the same
    98.
    发明授权
    Passivation layer assembly on a substrate and display substrate having the same 有权
    钝化层组件在基板上和具有该钝化层组件的显示基板上

    公开(公告)号：US07466026B2

    公开(公告)日：2008-12-16

    申请号：US11239716

    申请日：2005-09-29

    申请人： In-Ho Song ,  Kwan-young Cho ,  Ho Lee ,  Je-Min Lee

    发明人： In-Ho Song ,  Kwan-young Cho ,  Ho Lee ,  Je-Min Lee

    IPC分类号： H01L23/48 ,  H01L23/52

    CPC分类号： H01L29/458 ,  G02F1/136227 ,  H01L27/1244 ,  H01L27/1248

    摘要： A passivation layer assembly and a display substrate having the same are presented. The passivation layer assembly is positioned on a substrate having a thin film assembly and protects the thin film assembly. The thin film assembly includes a first passivation layer and a second passivation layer. The first passivation layer contacts the thin film assembly. The first passivation layer has a first etching rate with respect to an etching agent. The second passivation layer is on the first passivation layer. The second passivation layer has a second etching rate that is higher than the first etching rate with respect to the etching agent. The passivation assembly decrease the malfunction rate of the display device.

    摘要翻译： 提出了一种钝化层组件及其显示基板。 钝化层组件定位在具有薄膜组件的基底上，并保护薄膜组件。 薄膜组件包括第一钝化层和第二钝化层。 第一钝化层接触薄膜组件。 第一钝化层相对于蚀刻剂具有第一蚀刻速率。 第二钝化层位于第一钝化层上。 第二钝化层具有相对于蚀刻剂高于第一蚀刻速率的第二蚀刻速率。 钝化组件降低了显示设备的故障率。