公开(公告)号：US20180095881A1

公开(公告)日：2018-04-05

申请号：US15282444

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Eliezer Weissmann ,  Michael Mishaeli

IPC: G06F12/0815

CPC classification number: G06F9/30138 ,  G06F9/30043 ,  G06F9/30112 ,  G06F9/3012 ,  G06F9/50

Abstract: A system for communication using a register management array circuit is disclosed, including a processor, including a processing core, the processing core including a local core register, a register management array circuit coupled to the local core register, and a remote circuit coupled to the register management array circuit, the remote circuit including a remote register. The register management array circuit includes circuitry to cause the data in the local core register to match the data in the remote register. Methods and circuits are also disclosed.

公开(公告)号：US09678807B2

公开(公告)日：2017-06-13

申请号：US14107149

申请日：2013-12-16

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Lihu Rappoport

IPC: G06F9/50 ,  G06F1/32

CPC classification number: G06F9/5094 ,  G06F1/324 ,  G06F1/329 ,  G06F1/3293 ,  Y02D10/122 ,  Y02D10/126 ,  Y02D10/22 ,  Y02D10/24

Abstract: Hybrid threading in a processor is described. An integrated circuit that implements hybrid threading includes a power control unit (PCU), a first functional hardware unit coupled to the PCU, and a second functional hardware unit coupled to the PCU. The first functional hardware unit and the second functional hardware unit are heterogeneous functional hardware units. The PCU is configured to monitor at least one power attribute of the first and second functional hardware units. The PCU is further configured to calculate an aggregate power value based on the monitored at least one power attribute. Upon determining that the aggregate power value is below a power threshold, the PCU is also configured to calculate a first frequency for the first functional hardware unit and a second frequency for the second functional hardware unit that results in an updated aggregate power value that is closer to the power threshold.

公开(公告)号：US09639134B2

公开(公告)日：2017-05-02

申请号：US14614712

申请日：2015-02-05

Applicant: Intel Corporation

Inventor： Alexander Gendler

IPC: G06F1/26 ,  G06F1/32

CPC classification number: G06F1/3203 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: In an embodiment, a processor includes a plurality of cores including a first core. The first core includes a first plurality of accumulator logics, each accumulator logic of the first plurality of accumulator logics to store corresponding first core telemetry data. The processor also includes a power management unit (PMU) to request telemetry data from the first core and in response to receive the first core telemetry data stored in at least one accumulator logic of the first plurality of accumulator logics. Other embodiments are described and claimed.

公开(公告)号：US09535476B2

公开(公告)日：2017-01-03

申请号：US14497549

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： Shani Rehana ,  Alexander Gendler ,  Larisa Novakovsky

IPC: G06F1/12 ,  G06F3/06 ,  G06F5/06 ,  G06F1/26 ,  G06F5/10

CPC classification number: G06F1/26 ,  G06F1/12 ,  G06F3/0656 ,  G06F5/10 ,  G06F15/17331

Abstract: In an embodiment, a processor includes a first domain to operate according to a first clock. The first domain includes a write source, a payload bubble generator first in first out buffer (payload BGF) to store data packets, and write credit logic to maintain a count of write credits. The processor also includes a second domain to operate according to a second clock. When the write source has a data packet to be stored while the second clock is shut down, the write source is to write the data packet to the payload BGF responsive to the count of write credits being at least one, and after the second clock is restarted the second domain is to read the data packet from the payload BGF. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括根据第一时钟进行操作的第一域。 第一域包括首先在先出缓冲器（有效载荷BGF）中存储数据分组的写入源，有效负载气泡生成器，以及写入信用逻辑以维持写入信用的计数。 处理器还包括第二域，以便按照第二时钟进行操作。 当写入源具有在第二时钟关闭时要存储的数据包时，写入源将数据包写入有效载荷BGF，响应于至少一个写入信用的计数，并且在第二个时钟为 重新启动第二个域是从有效载荷BGF读取数据包。 描述和要求保护其他实施例。

公开(公告)号：US20160378133A1

公开(公告)日：2016-12-29

申请号：US14751875

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Kosta Luria ,  Arye Albahari ,  Ohad Nachshon

IPC: G06F1/10 ,  G01R19/165

CPC classification number: G06F1/08 ,  G01R1/203 ,  G01R19/0092 ,  G01R19/16528 ,  G01R19/16533 ,  G06F1/06 ,  G06F1/26

Abstract: A method and apparatus for performing current control for an integrated circuit are described. In one embodiment the apparatus comprises core logic coupled to receive a first current; a clock generator to generate a first clock signal; and a closed loop current controller coupled to the clock generator and coupled to provide a second clock signal to the core logic based on the first clock signal, the current controller to control an amount of the first current received by the core logic by changing the first clock signal to generate the second clock signal.

Abstract translation: 描述用于对集成电路进行电流控制的方法和装置。 在一个实施例中，该装置包括耦合以接收第一电流的核心逻辑; 时钟发生器，用于产生第一时钟信号; 以及闭环电流控制器，其耦合到所述时钟发生器并被耦合以基于所述第一时钟信号向所述核心逻辑提供第二时钟信号，所述电流控制器通过改变所述第一时钟信号来控制由所述核心逻辑接收的所述第一电流的量 时钟信号以产生第二时钟信号。

公开(公告)号：US09471088B2

公开(公告)日：2016-10-18

申请号：US13925986

申请日：2013-06-25

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Efraim Rotem ,  Julius Mandelblat ,  Alexander Lyakhov ,  Larisa Novakovsky ,  George Leifman ,  Lev Makovsky ,  Ariel Sabba ,  Niv Tokman

IPC: G06F1/08 ,  G06F1/04 ,  G06F1/32

CPC classification number: G06F1/08 ,  G06F1/04 ,  G06F1/32

Abstract: In an embodiment, a processor includes a core to execute instructions, where the core includes a clock generation logic to receive and distribute a first clock signal to a plurality of units of the core, a restriction logic to receive a restriction command and to reduce delivery of the first clock signal to at least one of the plurality of units. The restriction logic may cause the first clock signal to be distributed to the plurality of units at a lower frequency than a frequency of the first clock signal. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括用于执行指令的核心，其中核心包括时钟生成逻辑，用于接收和分配第一时钟信号到核心的多个单元，用于接收限制命令并减少传送的限制逻辑 的第一时钟信号发送到多个单元中的至少一个。 限制逻辑可以使得第一时钟信号以比第一时钟信号的频率低的频率被分配到多个单元。 描述和要求保护其他实施例。

公开(公告)号：US09377836B2

公开(公告)日：2016-06-28

申请号：US13951646

申请日：2013-07-26

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  George Leifman

IPC: G06F1/32 ,  G06F1/08 ,  G06F1/10 ,  G06F12/08 ,  G06F11/34

CPC classification number: G06F1/3206 ,  G06F1/08 ,  G06F1/10 ,  G06F1/3225 ,  G06F11/3024 ,  G06F11/34 ,  G06F11/3433 ,  G06F12/0811 ,  G06F12/084 ,  G06F2212/1028 ,  Y02D10/13

Abstract: In an embodiment, a processor has a core to execute instructions which includes a first cache memory, a clock generation logic to receive and distribute a first clock signal to a plurality of units of the core, and a core activity monitor logic to monitor activity of the core and, responsive to a miss in the first cache memory, to send a first restriction command to cause the clock generation logic to reduce delivery of the first clock signal to at least one of the units to a first frequency less than a frequency of the first clock signal. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器具有执行指令的核心，该指令包括第一高速缓存存储器，用于接收和分配第一时钟信号到第一时钟信号到核心的多个单元的时钟生成逻辑，以及用于监视活动的核心活动监视器逻辑 所述核心并且响应于所述第一高速缓冲存储器中的未命中，发送第一限制命令以使所述时钟产生逻辑将所述第一时钟信号的传送减少到所述至少一个所述单元的第一频率小于 第一个时钟信号。 描述和要求保护其他实施例。

公开(公告)号：US09104542B2

公开(公告)日：2015-08-11

申请号：US13730750

申请日：2012-12-28

Applicant: Intel Corporation

Inventor： Ariel Szapiro ,  Alexander Gendler

IPC: G06F11/10 ,  G06F11/00

CPC classification number: G06F11/006 ,  G06F11/1064

Abstract: A method is described that includes reading a cache tag and the cache tag's corresponding ECC from storage circuitry of a cache. The method also includes generating an ECC for a search tag. The method also includes calculating a hamming distance between a) the cache tag and its corresponding ECC and b) the search tag and its corresponding ECC. The method also includes determining if the cache tag matches the search tag by determining if said hamming distance is two or less.

Abstract translation: 描述了一种方法，其包括从高速缓存的存储电路读取高速缓存标签和高速缓存标签的相应的ECC。 该方法还包括生成用于搜索标签的ECC。 该方法还包括计算a）高速缓存标签与其对应的ECC之间的汉明距离，以及b）搜索标签及其对应的ECC。 该方法还包括通过确定所述汉明距离是否为2或更小来确定高速缓存标签是否与搜索标签相匹配。