公开(公告)号：US20210210679A1

公开(公告)日：2021-07-08

申请号：US16735020

申请日：2020-01-06

Applicant: International Business Machines Corporation

Inventor： Chi-Chun Liu ,  Yann Mignot ,  Ekmini Anuja De Silva ,  Nelson Felix ,  John Christopher Arnold

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02

Abstract: A method of forming a semiconductor structure includes forming a memorization layer over a substrate, forming a first self-aligned double patterning (SADP) stack including a first organic planarization layer (OPL), masking layer, set of mandrels, and set of spacers, and forming a patterned memorization layer by transferring a first pattern of the first set of spacers to the memorization layer. The method also includes forming a second SADP stack comprising a second OPL, masking layer, set of mandrels, and set of spacers, and forming an array of pillars by transferring a second pattern of the second set of spacers to the patterned memorization layer. The first and second OPL and the first and second sets of mandrels are a spin-on coated OPL material, and the memorization layer and first and second masking layers are a material configured for removal selective to the spin-on coated OPL material.

公开(公告)号：US20210151565A1

公开(公告)日：2021-05-20

申请号：US17134868

申请日：2020-12-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Chi-Chun Liu ,  Cheng Chi ,  Kangguo Cheng

IPC: H01L29/10 ,  H01L21/02 ,  H01L29/16 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L21/308

Abstract: Semiconductor devices include channel structures, arranged in vertically aligned pairs of channel structures. A gate stack is formed around all of the plurality of channel structures, filling a space between each pair of channel structures. Inner spacers are formed at respective ends of the channel structures, each having a vertical central portion and horizontal portions that extend outward from sides of the central portion, between the channels.

公开(公告)号：US10949601B2

公开(公告)日：2021-03-16

申请号：US16729706

申请日：2019-12-30

Applicant: International Business Machines Corporation

Inventor： Michael A. Guillorn ,  Kafai Lai ,  Chi-Chun Liu ,  Ananthan Raghunathan ,  Hsinyu Tsai

IPC: G06F30/398 ,  G06F30/39 ,  H01L29/66 ,  G06F119/18

Abstract: A method for reducing chemo-epitaxy directed-self assembly (DSA) defects of a layout of a guiding pattern, the method comprising expanding a shape of the guiding pattern by a predetermined distance in both lateral directions to form a fin keep mask, where the fin keep mask comprises a stand-alone mask.

公开(公告)号：US10755963B2

公开(公告)日：2020-08-25

申请号：US16170358

申请日：2018-10-25

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Chi-Chun Liu ,  Yann Mignot ,  Muthumanickam Sankarapandian

IPC: H01L21/762 ,  H01L29/66 ,  H01L21/265 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311

Abstract: A method for forming a silicon structure. A non-limiting example of the method includes forming at least two semiconductor fins on a substrate. A polymer brush material is formed over the fins and the substrate. A block copolymer (BCP) composed of a first polymer and a second polymer which are covalently bound together is applied over the polymer brush material, such that the first polymer and second polymer self-assemble into a plurality of interleaved first microdomains and second microdomains perpendicular to and within a trench between the fins. The first microdomains are composed of the first polymer and the second microdomains are composed of the second polymer. The second microdomains can be selectively removed.

公开(公告)号：US10755928B2

公开(公告)日：2020-08-25

申请号：US16258347

申请日：2019-01-25

Applicant: International Business Machines Corporation

Inventor： Chi-Chun Liu ,  Kristin Schmidt ,  Yann Mignot ,  Martha Inez Sanchez ,  Daniel Paul Sanders ,  Nelson Felix ,  Ekmini Anuja De Silva

IPC: H01L21/033 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3105

Abstract: A plurality of mandrels and silicon dioxide spacer structures are formed, with the spacer structures interdigitated between the mandrels. An organic planarization layer is applied, as are a thin oxide layer and a layer of photoresist patterned in hole tone over the oxide layer, thereby defining a domain. At least one hole is etched in the thin oxide layer and the organic planarization layer to expose a portion of a hard mask layer surface between the spacer structures. A selective polymer brush is applied, which grafts only to the exposed hard mask surface, followed by solvent rinsing the domain to remove ungrafted polymer brush. At least one precursor is infused to an etch resistant material into the polymer brush by a sequential infiltration synthesis process. The organic planarization layer is ashed to convert the infused precursor into oxide form to further enhance etch selectivity to the hard mask layer.

公开(公告)号：US10741681B2

公开(公告)日：2020-08-11

申请号：US16737242

申请日：2020-01-08

Applicant: International Business Machines Corporation

Inventor： Chi-Chun Liu ,  Chun Wing Yeung ,  Chen Zhang

IPC: H01L29/76 ,  H01L29/66 ,  H01L21/311 ,  H01L21/02 ,  H01L29/16 ,  H01L21/308 ,  H01L29/04 ,  H01L29/20 ,  H01L21/768

Abstract: The present invention provides a method and a structure of increasing source and drain contact edge width in a two-dimensional material field effect transistor. The method includes patterning a two-dimensional material over an insulating substrate; depositing a gate dielectric over the two-dimensional material; depositing a top gate over the gate dielectric, wherein the top gate has a hard mask thereon; forming a sidewall spacer around the top gate; depositing an interlayer dielectric oxide over the sidewall spacer and the hard mask; removing the interlayer dielectric oxide adjacent to the sidewall spacer to form an open contact trench; depositing a copolymer coating in the contact trench region; annealing the copolymer to induce a directed self-assembly; performing a two-dimensional material etch over the two-dimensional material; removing the unetched copolymer without etching the gate dielectric; and etching the exposed gate in the source and the drain region to form a metal contact layer.

公开(公告)号：US20200243335A1

公开(公告)日：2020-07-30

申请号：US16258347

申请日：2019-01-25

Applicant: International Business Machines Corporation

Inventor： Chi-Chun Liu ,  Kristin Schmidt ,  Yann Mignot ,  Martha Inez Sanchez ,  Daniel Paul Sanders ,  Nelson Felix ,  Ekmini Anuja De Silva

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/02

Abstract: A plurality of mandrels and silicon dioxide spacer structures are formed, with the spacer structures interdigitated between the mandrels. An organic planarization layer is applied, as are a thin oxide layer and a layer of photoresist patterned in hole tone over the oxide layer, thereby defining a domain. At least one hole is etched in the thin oxide layer and the organic planarization layer to expose a portion of a hard mask layer surface between the spacer structures. A selective polymer brush is applied, which grafts only to the exposed hard mask surface, followed by solvent rinsing the domain to remove ungrafted polymer brush. At least one precursor is infused to an etch resistant material into the polymer brush by a sequential infiltration synthesis process. The organic planarization layer is ashed to convert the infused precursor into oxide form to further enhance etch selectivity to the hard mask layer.

公开(公告)号：US20200144406A1

公开(公告)日：2020-05-07

申请号：US16737242

申请日：2020-01-08

Applicant: International Business Machines Corporation

Inventor： Chi-Chun Liu ,  Chun Wing Yeung ,  Chen Zhang

IPC: H01L29/76 ,  H01L29/66 ,  H01L21/311 ,  H01L21/02 ,  H01L21/768 ,  H01L21/308 ,  H01L29/04 ,  H01L29/20 ,  H01L29/16

Abstract: The present invention provides a method and a structure of increasing source and drain contact edge width in a two-dimensional material field effect transistor. The method includes patterning a two-dimensional material over an insulating substrate; depositing a gate dielectric over the two-dimensional material; depositing a top gate over the gate dielectric, wherein the top gate has a hard mask thereon; forming a sidewall spacer around the top gate; depositing an interlayer dielectric oxide over the sidewall spacer and the hard mask; removing the interlayer dielectric oxide adjacent to the sidewall spacer to form an open contact trench; depositing a copolymer coating in the contact trench region; annealing the copolymer to induce a directed self-assembly; performing a two-dimensional material etch over the two-dimensional material; removing the unetched copolymer without etching the gate dielectric; and etching the exposed gate in the source and the drain region to form a metal contact layer.

公开(公告)号：US10580886B2

公开(公告)日：2020-03-03

申请号：US15991023

申请日：2018-05-29

Applicant: International Business Machines Corporation

Inventor： Chi-Chun Liu ,  Chun Wing Yeung ,  Chen Zhang

IPC: H01L29/06 ,  H01L29/76 ,  H01L29/16 ,  H01L29/20 ,  H01L29/04 ,  H01L21/308 ,  H01L29/66 ,  H01L21/768 ,  H01L21/02 ,  H01L21/311

Abstract: The present invention provides a method and a structure of increasing source and drain contact edge width in a two-dimensional material field effect transistor. The method includes patterning a two-dimensional material over an insulating substrate; depositing a gate dielectric over the two-dimensional material; depositing a top gate over the gate dielectric, wherein the top gate has a hard mask thereon; forming a sidewall spacer around the top gate; depositing an interlayer dielectric oxide over the sidewall spacer and the hard mask; removing the interlayer dielectric oxide adjacent to the sidewall spacer to form an open contact trench; depositing a copolymer coating in the contact trench region; annealing the copolymer to induce a directed self-assembly; performing a two-dimensional material etch over the two-dimensional material; removing the unetched copolymer without etching the gate dielectric; and etching the exposed gate in the source and the drain region to form a metal contact layer.

公开(公告)号：US20200050108A1

公开(公告)日：2020-02-13

申请号：US16101411

申请日：2018-08-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chi-Chun Liu ,  Indira Seshadri ,  Kristin Schmidt ,  Nelson Felix ,  Daniel Sanders ,  Jing Guo ,  Ekmini Anuja De Silva ,  Hoa Truong

IPC: G03F7/11 ,  G03F7/004 ,  G03F7/09

Abstract: A self-priming resist may be formed from a first random copolymer forming a resist and a polymer brush having the general formula poly(A-r-B)-C-D, wherein A is a first polymer unit, B is a second polymer unit, wherein A and B are the same or different polymer units, C is a cleavable unit, D is a grafting group and r indicates that poly(A-r-B) is a second random copolymer formed from the first and second polymer units. The first random copolymer may be the same or different from the second random polymer. The self-priming resist can create a one-step method for forming an adhesion layer and resist by using the resist/brush blend.