Techniques for Vertical FET Gate Length Control

    公开(公告)号:US20190237562A1

    公开(公告)日:2019-08-01

    申请号:US15886539

    申请日:2018-02-01

    摘要: Techniques for VFET gate length control are provided. In one aspect, a method of forming a VFET device includes: patterning fins in a substrate; forming first polymer spacers alongside opposite sidewalls of the fins; forming second polymer spacers offset from the fins by the first polymer spacers; removing the first polymer spacers selective to the second polymer spacers; reflowing the second polymer spacers to close a gap to the fins; forming a cladding layer above the second polymer spacers; removing the second polymer spacers; forming gates along opposite sidewalls of the fins exposed in between the bottom spacers and the cladding layer, wherein the gates have a gate length Lg set by removal of the second polymer spacers; forming top spacers above the cladding layer; and forming top source and drains above the top spacers. A VFET device is also provided.

    Pattern-forming method
    4.
    发明授权

    公开(公告)号:US09847232B1

    公开(公告)日:2017-12-19

    申请号:US15468772

    申请日:2017-03-24

    摘要: A pattern-forming method includes forming a base pattern having recessed portions on a front face side of a substrate. A first composition is applied on lateral faces of the recessed portions of the base pattern, to form a coating. The first composition includes a first polymer which includes on at least one end of a main chain thereof a group capable of interacting with the base pattern. A surface of the coating is contacted with a highly polar solvent. The recessed portions are filled with a second composition. The second composition includes a second polymer which is capable of forming a phase separation structure through directed self-assembly. Phase separation is permitted in the second composition to form phases. A part of the phases is removed to form a miniaturized pattern. The substrate is etched directly or indirectly using the miniaturized pattern as a mask.