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    Gate stack of boron semiconductor alloy, polysilicon and high-K gate dielectric for low voltage applications
    93.
    发明授权
    Gate stack of boron semiconductor alloy, polysilicon and high-K gate dielectric for low voltage applications 有权
    硼半导体合金的栅堆叠，用于低电压应用的多晶硅和高K栅极电介质

    公开(公告)号：US08928064B2

    公开(公告)日：2015-01-06

    申请号：US14030520

    申请日：2013-09-18

    Applicant: International Business Machines Corporation

    Inventor： Martin M. Frank ,  Isaac Lauer ,  Jeffrey W. Sleight

    IPC: H01L29/51 ,  H01L29/78

    CPC classification number: H01L29/511 ,  H01L21/28044 ,  H01L21/2807 ,  H01L29/42364 ,  H01L29/4925 ,  H01L29/517 ,  H01L29/78

    Abstract: A method of forming a gate structure for a semiconductor device that includes forming a non-stoichiometric high-k gate dielectric layer on a semiconductor substrate, wherein an oxide containing interfacial layer can be present between the non-stoichiometric high-k gate dielectric layer and the semiconductor substrate. At least one gate conductor layer may be formed on the non-stoichiometric high-k gate dielectric layer. The at least one gate conductor layer comprises a boron semiconductor alloy layer. An anneal process is applied, wherein during the anneal process the non-stoichiometric high-k gate dielectric layer removes oxide material from the oxide containing interfacial layer. The oxide containing interfacial layer is thinned by removing the oxide material during the anneal process.

    Abstract translation: 一种形成半导体器件的栅极结构的方法，包括在半导体衬底上形成非化学计量的高k栅极电介质层，其中含有界面层的氧化物可以存在于非化学计量的高k栅极电介质层和 半导体衬底。 可以在非化学计量的高k栅极电介质层上形成至少一个栅极导体层。 所述至少一个栅极导体层包括硼半导体合金层。 应用退火工艺，其中在退火工艺期间，非化学计量的高k栅极电介质层从含氧化物界面层去除氧化物材料。 通过在退火过程中除去氧化物材料，使含氧化物的界面层变薄。

    MULTI-DIRECTION WIRING FOR REPLACEMENT GATE LINES
    94.
    发明申请
    MULTI-DIRECTION WIRING FOR REPLACEMENT GATE LINES 有权
    用于替代门电线的多方向接线

    公开(公告)号：US20140339639A1

    公开(公告)日：2014-11-20

    申请号：US13897568

    申请日：2013-05-20

    Applicant: International Business Machines Corporation

    Inventor： Josephine B. Chang ,  Michael A. Guillorn ,  Isaac Lauer ,  Jeffrey W. Sleight

    IPC: H01L21/28 ,  H01L29/66 ,  H01L29/78

    CPC classification number: H01L21/28008 ,  H01L21/762 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

    Abstract: A post-planarization recess etch process is employed in combination with a replacement gate scheme to enable formation of multi-directional wiring in gate electrode lines. After formation of disposable gate structures and a planarized dielectric layer, a trench extending between two disposable gate structures are formed by a combination of lithographic methods and an anisotropic etch. End portions of the trench overlap with the two disposable gate structures. After removal of the disposable gate structures, replacement gate structures are formed in gate cavities and the trench simultaneously. A contiguous gate level structure can be formed which include portions that extend along different horizontal directions.

    Abstract translation: 采用后平面化凹槽蚀刻工艺与替代栅极方案组合以使得能够在栅电极线中形成多方向布线。 在形成一次性栅极结构和平坦化介电层之后，通过光刻方法和各向异性蚀刻的组合形成在两个一次性栅极结构之间延伸的沟槽。 沟槽的端部与两个一次性栅极结构重叠。 在去除一次性栅极结构之后，替换栅极结构同时形成在栅极腔和沟槽中。 可以形成包括沿不同水平方向延伸的部分的连续门级结构。

    SELF-ALIGNED BORDERLESS CONTACTS USING A PHOTO-PATTERNABLE DIELECTRIC MATERIAL AS A REPLACEMENT CONTACT
    95.
    发明申请
    SELF-ALIGNED BORDERLESS CONTACTS USING A PHOTO-PATTERNABLE DIELECTRIC MATERIAL AS A REPLACEMENT CONTACT 有权
    使用光电导体材料作为替换接点的自对准边界接触

    公开(公告)号：US20140312397A1

    公开(公告)日：2014-10-23

    申请号：US14028022

    申请日：2013-09-16

    Applicant: International Business Machines Corporation

    Inventor： Szu-lin Cheng ,  Jack O. Chu ,  Isaac Lauer ,  Jeng-bang Yau

    IPC: H01L29/417

    CPC classification number: H01L21/283 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L29/41775 ,  H01L29/41791 ,  H01L29/665 ,  H01L29/66575 ,  H01L29/66795 ,  H01L29/785

    Abstract: A photo-patternable dielectric material is provided to a structure which includes a substrate having at least one gate structure. The photo-patternable dielectric material is then patterned forming a plurality of sacrificial contact structures adjacent the at least one gate structure. A planarized middle-of-the-line dielectric material is then provided in which an uppermost surface of each of the sacrificial contact structures is exposed. Each of the exposed sacrificial contact structures is then removed providing contact openings within the planarized middle-of-the-line dielectric material. A conductive metal-containing material is formed within each contact opening.

    Abstract translation: 光学图案化介电材料被提供到包括具有至少一个栅极结构的基板的结构。 然后对可光致图案化的电介质材料进行构图，形成与所述至少一个栅极结构相邻的多个牺牲接触结构。 然后提供平面化的中间线介电材料，其中暴露每个牺牲接触结构的最上表面。 然后去除每个暴露的牺牲接触结构，在平坦化的中间线介电材料内提供接触开口。 在每个接触开口内形成含导电金属的材料。

    SACRIFICIAL REPLACEMENT EXTENSION LAYER TO OBTAIN ABRUPT DOPING PROFILE
    96.
    发明申请
    SACRIFICIAL REPLACEMENT EXTENSION LAYER TO OBTAIN ABRUPT DOPING PROFILE 审中-公开
    非常重要的替代延伸层可以获得ABRUPT DOPING PROFILE

    公开(公告)号：US20140252500A1

    公开(公告)日：2014-09-11

    申请号：US13791475

    申请日：2013-03-08

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Szu-Lin Cheng ,  Jack O. Chu ,  Isaac Lauer ,  Jeng-Bang Yau

    IPC: H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/7834 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66598 ,  H01L29/66636 ,  H01L29/7848

    Abstract: At least one gate structure having a first spacer located on a vertical sidewall thereof is provided on an uppermost surface of a semiconductor substrate. Exposed portions of the semiconductor substrate are then removed utilizing the at least one gate structure and first spacer as an etch mask. A sacrificial replacement material is formed on each recessed surface of the semiconductor substrate. Next, a second spacer is formed contacting the first spacer. Source/drain trenches are then provided by removing exposed portions of the sacrificial replacement material and an underlying portion of the semiconductor substrate. Remaining sacrificial replacement material located beneath the second spacer is removed providing an opening beneath the second spacer. A doped semiconductor material is formed within the source/drain trenches and the opening.

    Abstract translation: 至少一个具有位于其垂直侧壁上的第一间隔件的栅极结构设置在半导体衬底的最上表面上。 然后利用至少一个栅极结构和第一间隔物作为蚀刻掩模去除半导体衬底的暴露部分。 牺牲替代材料形成在半导体衬底的每个凹进表面上。 接下来，形成接触第一间隔件的第二间隔件。 然后通过去除牺牲替换材料的暴露部分和半导体衬底的下层部分来提供源极/漏极沟槽。 移除位于第二间隔件下面的剩余牺牲替代材料，提供第二间隔物下方的开口。 掺杂半导体材料形成在源极/漏极沟槽和开口内。

    GATE STACK INCLUDING A HIGH-K GATE DIELECTRIC THAT IS OPTIMIZED FOR LOW VOLTAGE APPLICATIONS
    97.
    发明申请
    GATE STACK INCLUDING A HIGH-K GATE DIELECTRIC THAT IS OPTIMIZED FOR LOW VOLTAGE APPLICATIONS 有权
    包括用于低电压应用优化的高K栅介质的栅极堆叠

    公开(公告)号：US20140252492A1

    公开(公告)日：2014-09-11

    申请号：US13793290

    申请日：2013-03-11

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Martin M. Frank ,  Isaac Lauer ,  Jeffrey W. Sleight

    IPC: H01L29/78 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66

    CPC classification number: H01L29/78 ,  H01L21/28035 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/8238 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/6659 ,  H01L29/7833

    Abstract: A method of forming a semiconductor device that includes forming a high-k gate dielectric layer on a semiconductor substrate, wherein an oxide containing interfacial layer can be present between the high-k gate dielectric layer and the semiconductor substrate. A scavenging metal stack may be formed on the high-k gate dielectric layer. An annealing process may be applied to the scavenging metal stack during which the scavenging metal stack removes oxide material from the oxide containing interfacial layer, wherein the oxide containing interfacial layer is thinned by removing of the oxide material. A gate conductor layer is formed on the high-k gate dielectric layer. The gate conductor layer and the high-k gate dielectric layer are then patterned to provide a gate structure. A source region and a drain region are then formed on opposing sides of the gate structure.

    Abstract translation: 一种形成半导体器件的方法，包括在半导体衬底上形成高k栅介质层，其中含有界面层的氧化物可以存在于高k栅介质层和半导体衬底之间。 清除金属堆叠可以形成在高k栅极电介质层上。 可以将清除金属堆叠的清除金属堆叠中的退火工艺应用于其中，其中清除金属堆叠从含氧化物的界面层去除氧化物材料，其中通过除去氧化物材料使含有氧化物的界面层变薄。 栅极导体层形成在高k栅介质层上。 然后对栅极导体层和高k栅极电介质层进行构图以提供栅极结构。 然后在栅极结构的相对侧上形成源极区域和漏极区域。

    Diode Structure and Method for FINFET Technologies
    98.
    发明申请
    Diode Structure and Method for FINFET Technologies 有权
    FINFET技术的二极管结构和方法

    公开(公告)号：US20140217506A1

    公开(公告)日：2014-08-07

    申请号：US13761430

    申请日：2013-02-07

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Josephine B. Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

    IPC: H01L29/66 ,  H01L27/12

    CPC classification number: H01L27/1211 ,  H01L21/845 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/861

    Abstract: A method of fabricating an electronic device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. An oxide layer is formed over the SOI layer. At least one first set and at least one second set of fins are patterned in the SOI layer and the oxide layer. A conformal gate dielectric layer is selectively formed on a portion of each of the first set of fins that serves as a channel region of a transistor device. A first metal gate stack is formed on the conformal gate dielectric layer over the portion of each of the first set of fins that serves as the channel region of the transistor device. A second metal gate stack is formed on a portion of each of the second set of fins that serves as a channel region of a diode device.

    Abstract translation: 一种制造电子装置的方法包括以下步骤。 提供了具有在BOX上的SOI层的SOI晶片。 在SOI层上形成氧化物层。 在SOI层和氧化物层中图案化至少一个第一组和至少一个第二组翅片。 在作为晶体管器件的沟道区域的第一组翅片的每一个的一部分上选择性地形成保形栅极电介质层。 第一金属栅极叠层形成在第一组散热片的每一个作为晶体管器件的沟道区域的部分上的保形栅极电介质层上。 在作为二极管装置的通道区域的第二组翅片的每一个的一部分上形成第二金属栅极堆叠。

    TARGET QUBIT DECOUPLING IN AN ECHOED CROSS-RESONANCE GATE
    99.
    发明公开
    TARGET QUBIT DECOUPLING IN AN ECHOED CROSS-RESONANCE GATE 审中-公开

    公开(公告)号：US20240235698A1

    公开(公告)日：2024-07-11

    申请号：US18322768

    申请日：2023-05-24

    Applicant: International Business Machines Corporation

    Inventor： Isaac Lauer ,  Neereja Sundaresan

    IPC: H04B10/90 ,  G06N10/00

    CPC classification number: H04B10/90 ,  G06N10/00

    Abstract: Systems, computer-implemented methods, and/or computer program products that can facilitate target qubit decoupling in an echoed cross-resonance gate are provided. According to an embodiment, a computer-implemented method can comprise receiving, by a system operatively coupled to a processor, both a cross-resonance pulse and a decoupling pulse at a target qubit. The cross-resonance pulse propagates to the target qubit via a control qubit. The computer-implemented method can further comprise receiving, by the system, a state inversion pulse at the control qubit. The computer-implemented method can further comprise receiving, by the system, both a phase-inverted cross-resonance pulse and a phase-inverted decoupling pulse at the target qubit. The phase-inverted cross-resonance pulse propagates to the target qubit via the control qubit.

    Qubit reset from excited states
    100.
    发明授权
    Qubit reset from excited states 有权

    公开(公告)号：US11586448B2

    公开(公告)日：2023-02-21

    申请号：US16861653

    申请日：2020-04-29

    Applicant: International Business Machines Corporation

    Inventor： Isaac Lauer ,  Oliver Dial ,  Matthias Steffen

    IPC: G06F9/4401 ,  H04B10/70 ,  G06N10/00 ,  G06N10/40

    Abstract: Techniques regarding resetting highly excited qubits are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise a reset component that can de-excite a qubit system to a target state by transitioning a population of a first excited state of the qubit system to a ground state and by applying a signal to the qubit system that transitions a population of a second excited state to the first excited state.

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