公开(公告)号：US20150048428A1

公开(公告)日：2015-02-19

申请号：US13966885

申请日：2013-08-14

Applicant: International Business Machines Corporation

Inventor： Szu-Lin Cheng ,  Jack Oon Chu ,  Isaac Lauer ,  Jeng-Bang Yau

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L27/088 ,  H01L21/02647 ,  H01L21/3065 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/267 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66568 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78

Abstract: A method for manufacturing a semiconductor device comprises growing a source/drain epitaxy region over a plurality of gates on a substrate, wherein a top surface of the source/drain epitaxy region is at a height above a top surface of each of the plurality of gates, forming at least one opening in the source/drain epitaxy region over a top surface of at least one gate, forming a silicide layer on the source/drain epitaxy region, wherein the silicide layer lines lateral sides of the at least one opening, depositing a dielectric layer on the silicide layer, wherein the dielectric layer is deposited in the at least one opening between the silicide layer on lateral sides of the at least one opening, etching the dielectric layer to form a contact area, and depositing a conductor in the contact area.

公开(公告)号：US20150014778A1

公开(公告)日：2015-01-15

申请号：US13940874

申请日：2013-07-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Cheng-Wei Cheng ,  Szu-Lin Cheng ,  Keith E. Fogel ,  Edward W. Kiewra ,  Amlan Majumdar ,  Devendra K. Sadana ,  Kuen-Ting Shiu ,  Yanning Sun

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5226 ,  H01L21/823807 ,  H01L21/823878 ,  H01L23/485 ,  H01L27/1207 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a device with a multi-tiered contact structure includes forming first contacts in via holes down to a first level, forming a dielectric capping layer over exposed portions of the first contacts and forming a dielectric layer over the capping layer. Via holes are opened in the dielectric layer down to the capping layer. Holes are opened in the capping layer through the via holes to expose the first contacts. Contact connectors and second contacts are formed in the via holes such that the first and second contacts are connected through the capping layer by the contact connectors to form multi-tiered contacts.

Abstract translation: 用于形成具有多层接触结构的器件的方法包括将通孔中的第一触点形成为第一级，在第一触点的暴露部分上形成电介质覆盖层，并在覆盖层上形成电介质层。 通孔在电介质层中向下开到封盖层。 孔通过通孔在封盖层中打开以露出第一触点。 接触连接器和第二触点形成在通孔中，使得第一和第二触点通过接触连接器通过覆盖层连接以形成多层接触。

公开(公告)号：US10170608B2

公开(公告)日：2019-01-01

申请号：US14754751

申请日：2015-06-30

Applicant: International Business Machines Corporation

Inventor： Szu-Lin Cheng ,  Michael A. Guillorn ,  Gen P. Lauer ,  Isaac Lauer

IPC: H01L29/06 ,  H01L29/775 ,  H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L29/10 ,  H01L29/40 ,  H01L29/78

Abstract: A semiconductor device includes a first source/drain region a second source/drain region, and a gate region interposed between the first and second source/drain regions. At least one nanowire has a first end anchored to the first source/drain region and an opposing second end anchored to the second source/drain region such that the nanowire is suspended above the wafer in the gate region. At least one gate electrode is in the gate region. The gate electrode contacts an entire surface of the nanowire to define a gate-all-around configuration. At least one pair of oxidized spacers surrounds the at least one gate electrode to electrically isolate the at least one gate electrode from the first and second source/drain regions.

公开(公告)号：US20170005180A1

公开(公告)日：2017-01-05

申请号：US14754751

申请日：2015-06-30

Applicant: International Business Machines Corporation

Inventor： Szu-Lin Cheng ,  Michael A. Guillorn ,  Gen P. Lauer ,  Isaac Lauer

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/423 ,  H01L29/40 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/1054 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/517 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78642 ,  H01L29/78654 ,  H01L29/78696

Abstract: A semiconductor device includes a first source/drain region a second source/drain region, and a gate region interposed between the first and second source/drain regions. At least one nanowire has a first end anchored to the first source/drain region and an opposing second end anchored to the second source/drain region such that the nanowire is suspended above the wafer in the gate region. At least one gate electrode is in the gate region. The gate electrode contacts an entire surface of the nanowire to define a gate-all-around configuration. At least one pair of oxidized spacers surrounds the at least one gate electrode to electrically isolate the at least one gate electrode from the first and second source/drain regions.

公开(公告)号：US10170609B2

公开(公告)日：2019-01-01

申请号：US14948509

申请日：2015-11-23

Applicant: International Business Machines Corporation

Inventor： Szu-Lin Cheng ,  Michael A. Guillorn ,  Gen P. Lauer ,  Isaac Lauer

IPC: H01L29/06 ,  H01L29/775 ,  H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L29/10 ,  H01L29/40 ,  H01L29/78

Abstract: A semiconductor device includes a first source/drain region a second source/drain region, and a gate region interposed between the first and second source/drain regions. At least one nanowire has a first end anchored to the first source/drain region and an opposing second end anchored to the second source/drain region such that the nanowire is suspended above the wafer in the gate region. At least one gate electrode is in the gate region. The gate electrode contacts an entire surface of the nanowire to define a gate-all-around configuration. At least one pair of oxidized spacers surrounds the at least one gate electrode to electrically isolate the at least one gate electrode from the first and second source/drain regions.

公开(公告)号：US09917057B2

公开(公告)日：2018-03-13

申请号：US15361757

申请日：2016-11-28

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Szu-Lin Cheng ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC: H01L23/532 ,  H01L21/311 ,  H01L21/02 ,  H01L21/768 ,  H01L21/324 ,  H01L23/528 ,  H01L21/3105

CPC classification number: H01L23/53228 ,  H01L21/02134 ,  H01L21/02282 ,  H01L21/02351 ,  H01L21/31056 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/324 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In one aspect, a method of forming a wiring layer on a wafer is provided which includes: depositing a HSQ layer onto the wafer; cross-linking a first portion(s) of the HSQ layer using e-beam lithography; depositing a hardmask material onto the HSQ layer; patterning the hardmask using optical lithography, wherein the patterned hardmask covers a second portion(s) of the HSQ layer; patterning the HSQ layer using the patterned hardmask in a manner such that i) the first portion(s) of the HSQ layer remain and ii) the second portion(s) of the HSQ layer covered by the patterned hardmask remain, wherein by way of the patterning step trenches are formed in the HSQ layer; and filling the trenches with a conductive material to form the wiring layer on the wafer.

公开(公告)号：US09558930B2

公开(公告)日：2017-01-31

申请号：US14458887

申请日：2014-08-13

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Szu-Lin Cheng ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC: H01L23/532 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L21/324 ,  H01L23/528

CPC classification number: H01L23/53228 ,  H01L21/02134 ,  H01L21/02282 ,  H01L21/02351 ,  H01L21/31056 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/324 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In one aspect, a method of forming a wiring layer on a wafer is provided which includes: depositing a HSQ layer onto the wafer; cross-linking a first portion(s) of the HSQ layer using e-beam lithography; depositing a hardmask material onto the HSQ layer; patterning the hardmask using optical lithography, wherein the patterned hardmask covers a second portion(s) of the HSQ layer; patterning the HSQ layer using the patterned hardmask in a manner such that i) the first portion(s) of the HSQ layer remain and ii) the second portion(s) of the HSQ layer covered by the patterned hardmask remain, wherein by way of the patterning step trenches are formed in the HSQ layer; and filling the trenches with a conductive material to form the wiring layer on the wafer.

Abstract translation: 一方面，提供了一种在晶片上形成布线层的方法，包括：将HSQ层沉积到晶片上; 使用电子束光刻术交联HSQ层的第一部分; 将硬掩模材料沉积到HSQ层上; 使用光学平版印刷图案化硬掩模，其中图案化的硬掩模覆盖HSQ层的第二部分; 使用图案化的硬掩模以使得i）HSQ层的第一部分保留并且ii）被图案化硬掩模覆盖的HSQ层的第二部分保留的方式图案化HSQ层，其中通过 图案化步骤沟槽形成在HSQ层中; 并用导电材料填充沟槽以在晶片上形成布线层。

公开(公告)号：US20170005188A1

公开(公告)日：2017-01-05

申请号：US14948509

申请日：2015-11-23

Applicant: International Business Machines Corporation

Inventor： Szu-Lin Cheng ,  Michael A. Guillorn ,  Gen P. Lauer ,  Isaac Lauer

IPC: H01L29/775 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L29/786

CPC classification number: H01L29/66795 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/1054 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/517 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78642 ,  H01L29/78654 ,  H01L29/78696

Abstract: A semiconductor device includes a first source/drain region a second source/drain region, and a gate region interposed between the first and second source/drain regions. At least one nanowire has a first end anchored to the first source/drain region and an opposing second end anchored to the second source/drain region such that the nanowire is suspended above the wafer in the gate region. At least one gate electrode is in the gate region. The gate electrode contacts an entire surface of the nanowire to define a gate-all-around configuration. At least one pair of oxidized spacers surrounds the at least one gate electrode to electrically isolate the at least one gate electrode from the first and second source/drain regions.

Abstract translation: 半导体器件包括第一源极/漏极区域，第二源极/漏极区域和插入在第一和第二源极/漏极区域之间的栅极区域。 至少一个纳米线具有锚定到第一源极/漏极区域的第一端和锚定到第二源极/漏极区域的相对的第二端，使得纳米线悬浮在栅极区域中的晶片上方。 至少一个栅极电极位于栅极区域中。 栅电极接触纳米线的整个表面以限定栅极全部配置。 至少一对氧化间隔物围绕至少一个栅电极，以将至少一个栅电极与第一和第二源极/漏极区电隔离。

公开(公告)号：US20160379820A1

公开(公告)日：2016-12-29

申请号：US14948541

申请日：2015-11-23

Applicant: International Business Machines Corporation

Inventor： Szu-Lin Cheng ,  Isaac Lauer ,  Kuen-Ting Shiu ,  Jeng-Bang Yau

IPC: H01L21/02 ,  H01L21/306

CPC classification number: H01L21/02455 ,  H01L21/02538 ,  H01L21/02614 ,  H01L21/30604 ,  H01L29/0642 ,  H01L29/20 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes a wafer having a bulk layer and a III-V buffer layer on an upper surface of the bulk layer. The semiconductor device further includes at least one semiconductor fin on the III-V buffer layer. The semiconductor fin includes a III-V channel portion. Either the wafer or the semiconductor fin includes an oxidized III-V portion interposed between the III-V channel portion and the III-V buffer layer to prevent current leakage to the bulk layer.

公开(公告)号：US20150221643A1

公开(公告)日：2015-08-06

申请号：US14686260

申请日：2015-04-14

Applicant: International Business Machines Corporation

Inventor： Szu-Lin Cheng ,  Jack Oon Chu ,  Isaac Lauer ,  Jeng-Bang Yau

IPC: H01L27/088 ,  H01L29/08 ,  H01L29/45 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L27/088 ,  H01L21/02647 ,  H01L21/3065 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/267 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66568 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78

Abstract: A method for manufacturing a semiconductor device comprises growing a source/drain epitaxy region over a plurality of gates on a substrate, wherein a top surface of the source/drain epitaxy region is at a height above a top surface of each of the plurality of gates, forming at least one opening in the source/drain epitaxy region over a top surface of at least one gate, forming a silicide layer on the source/drain epitaxy region, wherein the silicide layer lines lateral sides of the at least one opening, depositing a dielectric layer on the silicide layer, wherein the dielectric layer is deposited in the at least one opening between the silicide layer on lateral sides of the at least one opening, etching the dielectric layer to form a contact area, and depositing a conductor in the contact area.

Abstract translation: 一种制造半导体器件的方法包括在衬底上的多个栅极上生长源极/漏极外延区域，其中源极/漏极外延区域的顶表面在多个栅极中的每一个的顶表面上方的高度 ，在至少一个栅极的顶表面上在所述源/漏外延区域中形成至少一个开口，在所述源/漏外延区域上形成硅化物层，其中所述硅化物层划分所述至少一个开口的侧面，沉积 位于所述硅化物层上的电介质层，其中所述电介质层沉积在所述至少一个开口的侧面上的所述硅化物层之间的所述至少一个开口中，蚀刻所述电介质层以形成接触区域， 接触面积