公开(公告)号：US10684968B2

公开(公告)日：2020-06-16

申请号：US15623960

申请日：2017-06-15

Applicant: International Business Machines Corporation

Inventor： David D. Cadigan ,  Thomas J. Dewkett ,  Glenn D. Gilda ,  Patrick J. Meaney ,  Craig R. Walters

IPC: G06F13/16

Abstract: A processor implemented method for spreading data traffic across memory controllers with respect to conditions is provided. The processor implemented method includes determining whether the memory controllers are balanced. The processor implemented method includes executing a conditional spreading with respect to the conditions when the memory controllers are determined as unbalanced. The processor implemented method includes executing an equal spreading when the memory controllers are determined as balanced.

公开(公告)号：US10606692B2

公开(公告)日：2020-03-31

申请号：US15849396

申请日：2017-12-20

Applicant: International Business Machines Corporation

Inventor： Paul W. Coteus ,  Kyu-hyoun Kim ,  Luis A. Lastras-Montano ,  Warren E. Maule ,  Patrick J. Meaney ,  James A. O'Connor ,  Barry M. Trager

IPC: G06F11/10 ,  G11C29/52 ,  G11C7/10 ,  G11C29/04

Abstract: An embodiment includes a method for use in operating a memory chip, the method comprising: operating the memory chip with an increased burst length relative to a standard burst length of the memory chip; and using the increased burst length to access metadata during a given operation of the memory chip. Another embodiment includes a memory module, comprising a plurality of memory chips, each memory chip being operable with an increased burst length relative to a standard burst length of the memory chip, the increased burst length being used to access metadata during a given operation of the memory module.

公开(公告)号：US20200097359A1

公开(公告)日：2020-03-26

申请号：US16142440

申请日：2018-09-26

Applicant: International Business Machines Corporation

Inventor： James A. O'Connor ,  Barry M. Trager ,  Warren E. Maule ,  Brad W. Michael ,  Marc A. Gollub ,  Patrick J. Meaney

IPC: G06F11/10 ,  G11C29/52

Abstract: Embodiments of the present invention include a memory module that includes a plurality of memory devices and a memory buffer device. The memory devices are characterized as one of a high or low random bit error rate (RBER) memory device. The memory buffer device includes a read data interface to receive data read from a memory address on one of the memory devices, and common error correction logic to detect and correct error conditions in data read from both high RBER and low RBER memory devices. The memory buffer device also includes refresh rate logic configured to adjust a refresh rate based on the detected error conditions.

公开(公告)号：US20190188074A1

公开(公告)日：2019-06-20

申请号：US15849396

申请日：2017-12-20

Applicant: International Business Machines Corporation

Inventor： Paul W. Coteus ,  Kyu-hyoun Kim ,  Luis A. Lastras-Montano ,  Warren E. Maule ,  Patrick J. Meaney ,  James A. O'Connor ,  Barry M. Trager

IPC: G06F11/10 ,  G11C29/52

CPC classification number: G06F11/1044 ,  G06F11/1012 ,  G06F11/1064 ,  G11C29/52

Abstract: An embodiment includes a method for use in operating a memory chip, the method comprising: operating the memory chip with an increased burst length relative to a standard burst length of the memory chip; and using the increased burst length to access metadata during a given operation of the memory chip. Another embodiment includes a memory module, comprising a plurality of memory chips, each memory chip being operable with an increased burst length relative to a standard burst length of the memory chip, the increased burst length being used to access metadata during a given operation of the memory module.

公开(公告)号：US20190163362A1

公开(公告)日：2019-05-30

申请号：US15825867

申请日：2017-11-29

Applicant: International Business Machines Corporation

Inventor： Steven R. Carlough ,  Susan M. Eickhoff ,  Warren E. Maule ,  Patrick J. Meaney ,  Stephen J. Powell ,  Gary A. Van Huben ,  Jie Zheng

IPC: G06F3/06 ,  G06F12/06

Abstract: One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communication links. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. In one aspect, the data buffer circuit receives a next to be used store data tag from a Host wherein the store data tag specifies the data buffer location in the data buffer circuit to store data, and in response to receiving store data from the Host, moves the data received at the data buffer circuit into the data buffer pointed to by the previously received store data tag.

公开(公告)号：US10303545B1

公开(公告)日：2019-05-28

申请号：US15827285

申请日：2017-11-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Patrick J. Meaney ,  Christian Jacobi ,  Barry M. Trager

IPC: G06F11/10 ,  H03M13/09 ,  H03M13/15 ,  G11C29/52

Abstract: A memory system includes memory modules having a number of sets of memory devices including data memory devices for data and error correction code (ECC). The ECC memory devices carry ECC symbols in order to facilitate Redundant Array of Independent Memory (RAIM) functionalities for the memory modules. A host receives and decodes the ECC symbols and executes RAIM operations. The host and the memory modules are coupled by a number of channels, one channel per each set of the memory devices.

公开(公告)号：US20190158223A1

公开(公告)日：2019-05-23

申请号：US15817416

申请日：2017-11-20

Applicant: International Business Machines Corporation

Inventor： Steven R. Carlough ,  Patrick J. Meaney ,  Gary Van Huben

IPC: H04L1/00

Abstract: Aspects of the invention include using a cyclic redundancy code (CRC) multiple-input signature register (MISR) for early warning and fail detection. Received bits are monitored at a receiver for transmission errors. The monitoring includes receiving frames of bits that are a subset of frames of bits used by the transmitter to generate a multi-frame CRC. At least one of the received frames of bits includes payload bits and a source single check bit not included in the multi-frame CRC. It is determined whether a transmission error has occurred in the received frames of bits. The determining includes generating a calculated single check bit based at least in part on bits in the received frames of bits, and comparing the received source single check bit to the calculated single check bit. An error indication is transmitted to the transmitter if they don't match.

公开(公告)号：US20190079840A1

公开(公告)日：2019-03-14

申请号：US15702787

申请日：2017-09-13

Applicant: International Business Machines Corporation

Inventor： Marc A. Gollub ,  Warren E. Maule ,  Patrick J. Meaney

IPC: G06F11/20

Abstract: Aspects of the invention include fetching data requested by a requestor from a primary memory in a memory system that includes the primary memory and a secondary memory mirroring the primary memory. An error status of the data fetched from the primary memory is determined. The error status is one of correctable error (CE), uncorrectable error (UE), and no error. Based at least in part on determining that the data fetched from the primary memory has the error status of no error, the data fetched from the primary memory is output to the requestor. Based at least in part on determining that the data fetched from the primary memory has the error status of UE or CE, the data requested by the requestor is fetched from the secondary memory.

公开(公告)号：US20190020565A1

公开(公告)日：2019-01-17

申请号：US15651346

申请日：2017-07-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Luiz C. Alves ,  Patrick J. Meaney ,  Christopher N. Oelsner ,  Gary A. Peterson ,  Christopher Steffen

IPC: H04L12/26 ,  G06F13/42 ,  G06F13/40 ,  H04L12/24

Abstract: A technique relates to dynamic time-domain reflectometry (TDR). A machine spares a bad lane in a bus. The bad lane is taken offline. TDR is dynamically executed on the bad lane while the bus is still in operation. A defect is isolated using results of the TDR.

公开(公告)号：US20180367166A1

公开(公告)日：2018-12-20

申请号：US15830526

申请日：2017-12-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Glenn D. Gilda ,  Patrick J. Meaney ,  Arthur O'Neill ,  Barry M. Trager

IPC: H03M13/00 ,  H03M13/15

Abstract: Systems, methods, and computer-readable media are disclosed for performing reduced latency error decoding using a reduced latency symbol error correction decoder that utilizes enumerated parallel multiplication in lieu of division and replaces general multiplication with constant multiplication. The use of parallel multiplication in lieu of division can provide reduced latency and replacement of general multiplication with constant multiplication allows for logic reduction. In addition, the reduced symbol error correction decoder can utilize decode term sharing which can yield a further reduction in decoder logic and a further latency improvement.