公开(公告)号：US06570434B1

公开(公告)日：2003-05-27

申请号：US09662685

申请日：2000-09-15

申请人： Louis Hsu ,  Russell J. Houghton ,  Oliver Weinfurtner

发明人： Louis Hsu ,  Russell J. Houghton ,  Oliver Weinfurtner

IPC分类号： G05F302

CPC分类号： G11C5/145

摘要： A dynamic clamp is used in conjunction with capacitors with thinner dielectric or with deep trench capacitors to solve the problem of dielectric breakdown in high stress capacitors. The dynamic clamp is realized using a two stage pump operation cycle such that, during a first stage pump cycle, a middle node of a pair of series connected capacitors is pre-charged to a supply voltage and, during a second stage pump cycle, the middle node is coupled by a boost clock. Thus, at any moment in the pump operation cycle, the voltage across the capacitors is held within a safety range.

公开(公告)号：US06524908B2

公开(公告)日：2003-02-25

申请号：US09872603

申请日：2001-06-01

申请人： Cyril Cabral, Jr. ,  Lawrence Clevenger ,  Louis Hsu ,  Keith Kwong Hon Wong

发明人： Cyril Cabral, Jr. ,  Lawrence Clevenger ,  Louis Hsu ,  Keith Kwong Hon Wong

IPC分类号： H01L218242

CPC分类号： H01L28/75 ,  C23C14/0073 ,  C23C14/0641 ,  H01L21/2855 ,  H01L21/28568

摘要： A method forforming a refractory metal-silicon-nitrogen capacitor in a semiconductor structure and the structure formed are described. In the method, a pre-processed semiconductor substrate is first positioned in a sputtering chamber. Ar gas is then flown into the sputtering chamber to sputter deposit a first refractory metal-silicon-nitrogen layer on the substrate from a refractory metal silicide target, or from two targets of a refractory metal and a silicon. N2 gas is then flown into the sputtering chamber until that the concentration of N2 gas in the chamber is at least 35% to sputter deposit a second refractory metal-silicon-nitrogen layer on top of the first refractory metal-silicon-nitrogen layer. The N2 gas flow is then stopped to sputter deposit a third refractory metal-silicon-nitrogen layer on top of the second refractory metal-silicon-nitrogen layer. The multi-layer stack of the refractory metal-silicon-nitrogen is then photolithographically formed into a capacitor.

摘要翻译： 描述了一种在半导体结构中形成难熔金属 - 硅 - 氮电容器的方法和形成的结构。 在该方法中，首先将预处理的半导体衬底定位在溅射室中。 然后将Ar气体流入溅射室，以从耐火金属硅化物靶或从难熔金属和硅的两个靶溅射沉积在衬底上的第一难熔金属 - 硅 - 氮层。 然后将N 2气体流入溅射室，直到室内的N 2气体的浓度至少为35％，以在第一难熔金属 - 硅 - 氮层的顶部溅射沉积第二难熔金属 - 硅 - 氮层。 然后停止N 2气流以在第二难熔金属 - 硅 - 氮层的顶部溅射沉积第三难熔金属 - 硅 - 氮层。 然后将难熔金属硅 - 氮的多层堆叠光刻形成电容器。

公开(公告)号：US08024012B2

公开(公告)日：2011-09-20

申请号：US12137185

申请日：2008-06-11

申请人： Lawrence Clevenger ,  Timothy Dalton ,  Louis Hsu ,  Carl Radens

发明人： Lawrence Clevenger ,  Timothy Dalton ,  Louis Hsu ,  Carl Radens

IPC分类号： H04B1/38 ,  H04B1/16

CPC分类号： H02J50/20 ,  H02J7/025 ,  H02J17/00

摘要： A system and methodology for intelligent power management of wirelessly networked devices. The system provides for reliable wireless communication via a wireless power charging method and, a method to maintain power capacity of batteries in a wireless device. The batteries are charged via an RF harvesting unit embedded inside the wireless device. An intelligent wireless power charging system further comprises at least two batteries and at least two RF adaptor devices coupled to an AC power line. The first adaptor is set for data communication while the second adaptor is used to transmit the power. In addition, when a first battery is in use during active mode, the second battery is subjected to wireless charging.

摘要翻译： 一种用于无线网络设备智能电源管理的系统和方法。 该系统通过无线电力充电方法提供可靠的无线通信，以及在无线设备中维持电池的电力容量的方法。 电池通过嵌入在无线设备内部的射频收集单元进行充电。 智能无线电力充电系统还包括耦合到AC电力线的至少两个电池和至少两个RF适配器装置。 第一个适配器设置为数据通信，而第二个适配器用于传输电源。 此外，当在活动模式期间使用第一电池时，对第二电池进行无线充电。

公开(公告)号：US07851321B2

公开(公告)日：2010-12-14

申请号：US12348707

申请日：2009-01-05

申请人： Lawrence Clevenger ,  Timothy Joseph Dalton ,  Louis Hsu ,  Carl Radens ,  Vidhya Ramachandran ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

发明人： Lawrence Clevenger ,  Timothy Joseph Dalton ,  Louis Hsu ,  Carl Radens ,  Vidhya Ramachandran ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

IPC分类号： H01L21/20

CPC分类号： H01L21/84 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5223 ,  H01L27/1203 ,  H01L2924/0002 ,  Y10S438/957 ,  H01L2924/00

摘要： Methods are provided for fabricating semiconductor IC (integrated circuit) chips having high-Q on-chip capacitors formed on the chip back-side and connected to integrated circuits on the chip front-side using through-wafer interconnects. In one aspect, a semiconductor device includes a semiconductor substrate having a front side, a back side, and a buried insulating layer interposed between the front and back sides of the substrate. An integrated circuit is formed on the front side of the semiconductor substrate, an integrated capacitor is formed on the back side of the semiconductor substrate, and an interconnection structure is formed through the buried insulating layer to connect the integrated capacitor to the integrated circuit.

摘要翻译： 提供了用于制造半导体IC（集成电路）芯片的半导体IC（集成电路）芯片，其具有形成在芯片背面的高Q片上电容器，并使用晶片间互连连接到芯片正面的集成电路。 在一个方面，半导体器件包括一个半导体衬底，该半导体衬底具有介于衬底的正面和背面之间的正面，背面和掩埋绝缘层。 在半导体基板的正面形成有集成电路，在半导体基板的背面形成有集成电容器，通过埋入绝缘层形成互连结构，将集成电容器与集成电路连接起来。

公开(公告)号：US07676775B2

公开(公告)日：2010-03-09

申请号：US11754947

申请日：2007-05-29

申请人： Howard Chen ,  Katherine V. Hawkins ,  Fook-Luen Heng ,  Louis Hsu ,  Xu Ouyang

发明人： Howard Chen ,  Katherine V. Hawkins ,  Fook-Luen Heng ,  Louis Hsu ,  Xu Ouyang

IPC分类号： G06F17/50

CPC分类号： G01R31/2894 ,  G01R31/31718 ,  G01R31/318314 ,  G11C29/10 ,  G11C29/56 ,  G11C29/56008

摘要： A method for determining the root causes of fail patterns in integrated circuit chips is provide wherein a known integrated circuit chip layout is used to identify a plurality of potential defects and a plurality of potential fail patterns in the integrated circuit chip. Correlations between the potential defects and the potential fail patterns that result from those defects are identified. Based on this identification, the potential fail patterns are grouped by common potential defect. An actual integrated circuit chip that is manufactured in accordance with the test layout is tested for failure patterns. These failure patterns are then compared to the groupings of potential fail patterns. When a match is found, that is when a given group of fail patterns is found in the actual integrated circuit chip, then the potential defect associated with the potential fail patterns to which the actual fail patterns are matched is identified. This defect is the root cause of the failure pattern in the actual chip.

摘要翻译： 提供了一种用于确定集成电路芯片中的故障模式的根本原因的方法，其中使用已知的集成电路芯片布局来识别集成电路芯片中的多个潜在缺陷和多个潜在故障模式。 鉴定出潜在缺陷与由这些缺陷产生的潜在失效模式之间的相关性。 基于此识别，潜在的故障模式由共同的潜在缺陷分组。 测试根据测试布局制造的实际集成电路芯片的故障模式。 然后将这些故障模式与潜在故障模式的分组进行比较。 当发现匹配时，即在实际的集成电路芯片中发现给定的一组故障模式时，识别与实际故障模式匹配的潜在故障模式相关联的潜在缺陷。 这个缺陷是实际芯片中故障模式的根本原因。

公开(公告)号：US07486114B2

公开(公告)日：2009-02-03

申请号：US11383821

申请日：2006-05-17

申请人： Minhan Chen ,  Louis Hsu ,  Joseph Natonio ,  Karl D. Selander ,  Michael A. Sorna ,  Steven J. Zier

发明人： Minhan Chen ,  Louis Hsu ,  Joseph Natonio ,  Karl D. Selander ,  Michael A. Sorna ,  Steven J. Zier

IPC分类号： H03K5/19

CPC分类号： H04L25/0274 ,  H04L25/0296

摘要： A signal detector and method to detect the presence or absence of an incoming differential signal. The method nullifies the DC off-set of the signal detector so that it can detect a signal within a very narrow window. The common mode levels of the signal and reference paths are used for calibration which is done automatically by use of an embedded algorithm residing in a digital block. The calibration range and resolution are predetermined to cope with the technology, modeling, design methodology and human error.

摘要翻译： 一种用于检测输入差分信号的存在或不存在的信号检测器和方法。 该方法使信号检测器的DC偏移无效，使得其可以在非常窄的窗口内检测信号。 信号和参考路径的共模电平用于通过使用位于数字块中的嵌入式算法自动完成的校准。 预定校准范围和分辨率，以应对技术，建模，设计方法和人为错误。

公开(公告)号：US20080108220A1

公开(公告)日：2008-05-08

申请号：US11925161

申请日：2007-10-26

申请人： Chih-Chao Yang ,  Louis Hsu

发明人： Chih-Chao Yang ,  Louis Hsu

IPC分类号： H01L21/4763

CPC分类号： H01L21/76849 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure that includes a barrier-redundancy feature which is capable of avoiding a sudden open circuit after an electromigration (EM) failure as well as a method of forming the same are provided. In accordance with the present invention, the barrier-redundancy feature is located within preselected locations within the interconnect structure including in a wide line region, a thin line region or any combination thereof. The barrier-redundancy feature includes an electrical conductive material located between, and in contact with, a conductive line diffusion barrier of a conductive line and a via diffusion barrier of an overlying via. The presence of the inventive barrier-redundancy feature creates an electrical path between the via diffusion barrier along the sidewalls of the via and the conductive line diffusion barrier along the sidewalls of the conductive line. This electrical path generated by the inventive barrier-redundancy feature can avoid a sudden open circuit resulting from EM failure at the bottom of the via. The presence of the inventive barrier-redundancy feature within an interconnect structure provides sufficient time for chip replacement or system operation.

摘要翻译： 提供一种互连结构，其包括能够在电迁移（EM）故障之后避免突然断路的障碍物冗余特征以及其形成方法。 根据本发明，阻挡冗余特征位于互连结构内的预选位置，包括在宽线区域，细线区域或其任何组合中。 阻挡层冗余特征包括导电材料，其位于导电线的导电线扩散阻挡层和上覆通孔的通孔扩散阻挡层之间并与之接触。 本发明的阻挡 - 冗余特征的存在在沿着导电线的侧壁的通孔的侧壁和导电线扩散阻挡层之间形成通路扩散阻挡层之间的电路径。 由本发明的障碍物冗余特征产生的该电路径可以避免由于通孔底部的EM故障导致的突然开路。 在互连结构内部存在本发明的障碍物冗余特征为芯片更换或系统操作提供足够的时间。

公开(公告)号：US20080050890A1

公开(公告)日：2008-02-28

申请号：US11928456

申请日：2007-10-30

申请人： Louis Hsu ,  Jack Mandelman ,  William Tonti

发明人： Louis Hsu ,  Jack Mandelman ,  William Tonti

IPC分类号： H01L21/20

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L29/045

摘要： A semiconductor structure with an insulating layer on a silicon substrate, a plurality of electrically-isolated silicon-on-insulator (SOI) regions separated from the substrate by the insulating layer, and a plurality of electrically-isolated silicon bulk regions extending through the insulating layer to the substrate. Each of one number of the SOI regions is oriented with a first crystal orientation and each of another number of the SOI regions is oriented with a second crystal orientation that differs from the first crystal orientation. The bulk silicon regions are each oriented with a third crystal orientation. Damascene or imprinting methods of forming the SOI regions and bulk silicon regions are also provided.

摘要翻译： 一种在硅衬底上具有绝缘层的半导体结构，通过绝缘层从衬底分离出的多个电隔离绝缘体上硅（SOI）区域，以及延伸穿过绝缘体的多个电隔离硅体区域 层到基底。 SOI区域中的每一个以第一晶体取向取向，并且另外数量的SOI区域中的每一个以与第一晶体取向不同的第二晶体取向取向。 体硅区域各自定向为具有第三晶体取向。 还提供了形成SOI区域和体硅区域的镶嵌或印刷方法。

公开(公告)号：US20080049378A1

公开(公告)日：2008-02-28

申请号：US11927774

申请日：2007-10-30

申请人： Louis Hsu ,  Rajiv Joshi ,  Chun-Yung Sung

发明人： Louis Hsu ,  Rajiv Joshi ,  Chun-Yung Sung

IPC分类号： H01G4/20

CPC分类号： H01G4/228 ,  H01G4/33 ,  H01L21/768 ,  H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  Y10S438/957 ,  H01L2924/00

摘要： A metal-insulator-metal (MIM) capacitor including a metal layer, an insulating layer formed on the metal layer, at least a first opening and at least a second opening formed in the first insulating layer, a dielectric layer formed in the first opening, a conductive material deposited in the first and second openings, and a first metal plate formed over the first opening and a second metal plate formed over the second opening. A method for fabricating the MIM capacitor, includes forming the first metal layer, forming the insulating layer on the first metal layer, forming at least the first opening and at least the second opening in the first insulating layer, depositing a mask over the second opening, forming the dielectric layer in the first opening, removing the mask, depositing the conductive material in the first and second openings, and depositing a second metal layer over the first and second openings. MIM capacitors and methods of fabricating same are described, wherein the MIM capacitors are formed simultaneously with the BEOL interconnect and large density MIM capacitors are fabricated at low cost.

摘要翻译： 一种金属绝缘体金属（MIM）电容器，包括金属层，形成在金属层上的绝缘层，至少第一开口和形成在第一绝缘层中的至少第二开口，形成在第一开口中的电介质层 沉积在第一和第二开口中的导电材料和形成在第一开口上的第一金属板和形成在第二开口上的第二金属板。 一种制造MIM电容器的方法，包括形成第一金属层，在第一金属层上形成绝缘层，至少形成第一开口和至少第一绝缘层中的第二开口，在第二开口上沉积掩模 在第一开口中形成电介质层，去除掩模，在第一和第二开口中沉积导电材料，并在第一和第二开口上沉积第二金属层。 描述MIM电容器及其制造方法，其中MIM电容器与BEOL互连同时形成，并且以低成本制造大密度MIM电容器。

公开(公告)号：US07329600B2

公开(公告)日：2008-02-12

申请号：US10817179

申请日：2004-04-02

申请人： Lawrence Clevenger ,  Louis Hsu ,  Christy S. Tyberg ,  Tsorng-Dih Yuan

发明人： Lawrence Clevenger ,  Louis Hsu ,  Christy S. Tyberg ,  Tsorng-Dih Yuan

IPC分类号： H01L21/4763

CPC分类号： H01L23/5222 ,  H01L21/76829 ,  H01L21/76835 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A process for fabricating a low dielectric constant semiconductor comprising the steps of: depositing a first metal layer on a substrate; patterning the first metal layer to produce a patterned first metal wiring; applying a first insulating material onto the patterned first metal wiring to form a support structure; patterning the first insulating material by a contact printing process; depositing a second insulating material of lower dielectric constant onto the support structure; planarizing the second insulating material; depositing a polish-stop film layer over the planarized second insulating material, thereby forming a plurality of metal studs; depositing a second metal layer onto the polish-stop film layer forming interconnects with said studs; and patterning the metal layer to produce a second metal wiring interconnecting to the first wiring via the metal studs.

摘要翻译： 一种制造低介电常数半导体的方法，包括以下步骤：在衬底上沉积第一金属层; 图案化第一金属层以产生图案化的第一金属布线; 将第一绝缘材料施加到所述图案化的第一金属布线上以形成支撑结构; 通过接触印刷方法图案化第一绝缘材料; 将较低介电常数的第二绝缘材料沉积到所述支撑结构上; 平面化第二绝缘材料; 在平坦化的第二绝缘材料上沉积抛光停止膜层，从而形成多个金属螺柱; 将第二金属层沉积到所述抛光 - 停止膜层上，形成与所述螺柱的互连; 以及图案化所述金属层以产生经由所述金属螺柱与所述第一布线互连的第二金属布线。